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SN54AHC367J PDF预览

SN54AHC367J

更新时间： 2024-11-01 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
12页 345K
描述
HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

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SN54AHC367J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：N其他特性：ONE FUNCTION WITH TWO BITS
系列：AHCJESD-30 代码：R-GDIP-T16
长度：19.56 mm逻辑集成电路类型：BUS DRIVER
位数：6功能数量：1
端口数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：13.5 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54AHC367J 数据手册

 浏览型号SN54AHC367J的Datasheet PDF文件第2页浏览型号SN54AHC367J的Datasheet PDF文件第3页浏览型号SN54AHC367J的Datasheet PDF文件第4页浏览型号SN54AHC367J的Datasheet PDF文件第5页浏览型号SN54AHC367J的Datasheet PDF文件第6页浏览型号SN54AHC367J的Datasheet PDF文件第7页 
SN54AHC367, SN74AHC367  
HEX BUFFERS AND LINE DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS424E – JUNE 1998 – REVISED FEBRUARY 2002  
SN54AHC367 . . . J OR W PACKAGE  
SN74AHC367 . . . D, DB, DGV, N, OR PW PACKAGE  
(TOP VIEW)  
Operating Range 2-V to 5.5-V V  
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1OE  
1A1  
1Y1  
1A2  
1Y2  
1A3  
1Y3  
GND  
V
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
2OE  
2A2  
2Y2  
– 1000-V Charged-Device Model (C101)  
12 2A1  
description  
11  
10  
9
2Y1  
1A4  
1Y4  
The ’AHC367 devices are hex buffers and line  
drivers designed for 2-V to 5.5-V V operation.  
CC  
These devices are designed specifically to  
improve both the performance and density of  
3-state memory address drivers, clock drivers,  
and bus-oriented receivers and transmitters. The  
’AHC367 devices are organized as dual 4-line  
and 2-line buffers/drivers with active-low  
output-enable (1OE and 2OE) inputs. When OE is  
low, the device passes noninverted data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
SN54AHC367 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2A2  
2Y2  
NC  
1Y1  
1A2  
NC  
4
5
6
7
8
17  
16  
15 2A1  
14  
9 10 11 12 13  
1Y2  
1A3  
2Y1  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube  
SN74AHC367N  
SN74AHC367N  
Tube  
SN74AHC367D  
AHC367  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC367DR  
SN74AHC367DBR  
SN74AHC367PWR  
SN74AHC367DGVR  
SNJ54AHC367J  
SNJ54AHC367W  
SNJ54AHC367FK  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
CDIP – J  
HA367  
HA367  
HA367  
SNJ54AHC367J  
SNJ54AHC367W  
SNJ54AHC367FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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