Datasheet > SN5474LS114A

SN5474LS114A

更新时间： 2024-11-12 04:31:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
4页	149K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

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SN5474LS114A 数据手册

SN54/74LS114A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS114A offers common clock and common clear inputs and

individual J, K, and set inputs. These monolithic dual flip-flops are designed

so that when the clock goes HIGH, the inputs are enabled and data will be

accepted. ThelogicleveloftheJandKinputsmaybeallowedtochangewhen

the clock pulse is HIGH and the bistable will perform according to the truth

table as long as minimum set-up times are observed. Input data is transferred

to the outputs on the negative-going edge of the clock pulse.

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC DIAGRAM (Each Flip-Flop)

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

D SUFFIX

SOIC

CASE 751A-02

ORDERING INFORMATION

MODE SELECT — TRUTH TABLE

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

INPUTS

OUTPUTS

OPERATING MODE

Set

Reset (Clear)

*Undetermined

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

LOGIC SYMBOL

* BothoutputswillbeHIGHwhilebothS andC areLOW,buttheoutputstates

are unpredictable if S and C go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output)

l, h (q) = one set-up time prior to the HIGH to LOW clock transition.

FAST AND LS TTL DATA

5-193

12 3 4

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