Datasheet > SM65MLVD080DGGR

SM65MLVD080DGGR

更新时间： 2024-09-25 22:29:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
24页	237K
描述
8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS

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SM65MLVD080DGGR 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP64,.32,20	针数：	64
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.48
差分输出：	YES	驱动器位数：	8
高电平输入电流最大值：	0.00001 A	输入特性：	DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：	LINE TRANSCEIVER	接口标准：	EIA-899; TIA-899
JESD-30 代码：	R-PDSO-G64	长度：	17 mm
功能数量：	8	端子数量：	64
最高工作温度：	85 °C	最低工作温度：	-40 °C
最小输出摆幅：	0.48 V	最大输出低电流：	0.008 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP64,.32,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	3.3 V
认证状态：	Not Qualified	最大接收延迟：	6 ns
接收器位数：	8	座面最大高度：	1.2 mm
子类别：	Line Driver or Receivers	最大压摆率：	180 mA
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	最大传输延迟：	2.4 ns
宽度：	6.1 mm	Base Number Matches：	1

SM65MLVD080DGGR 数据手册

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www.ti.com

SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003

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multipoint buses presenting loads as low as 30-Ω and

incorporates controlled transition times to allow for stubs

off of the backbone transmission line.

FEATURES

Low-Voltage Differential 30-Ω to 55-Ω Line

Drivers and Receivers for Signaling Rates

(1)

The M-LVDS standard defines two types of receivers,

designated as Type-1 and Type-2. Type-1 receivers

(SN65MLVD080) have thresholds centered about zero

with 25 mV of hysteresis to prevent output oscillations with

loss of input; Type-2 receivers (SN65MLVD082)

implement a failsafe by using an offset threshold. In

addition, the driver rise and fall times are between 1 and

2.0 ns, complying with the M-LVDS standard to provide

operation at 250 Mbps while also accommodating stubs on

the bus. Receiver outputs are slew rate controlled to

reduce EMI and crosstalk effects associated with large

current surges. The M-LVDS standard allows for 32 nodes

on the bus providing a high-speed replacement for RS-485

where lower common-mode can be tolerated or when

higher signaling rates are needed.

Up to 250 Mbps; Clock Frequencies Up to 125

MHz

Meets or Exceeds the M-LVDS Standard

TIA/EIA-899 for Multipoint Data Interchange

Power Up/Down Glitch Free

Controlled Driver Output Voltage Transition

Times for Improved Signal Quality

−1 V to 3.4 V Common-Mode Voltage Range

Allows Data Transfer With 2 V of Ground

Noise

Bus Pins High Impedance When Driver

Disabled or V

≤ 1.5 V

Independent Enables for each Driver

Bus Pin ESD Protection Exceeds 8 kV

Packaged in 64-Pin TSSOP (DGG)

The driver logic inputs and the receiver logic outputs are

on separate pins rather than tied together as in some

transceiver designs. The drivers have separate enables

(DE) and the receivers are enabled globally through (RE).

This arrangement of separate logic inputs, logic outputs,

and enable pins allows for a listen-while-talking operation.

The devices are characterized for operation from −40°C to

85°C.

APPLICATIONS

Parallel Multipoint Data and Clock

Transmission Via Backplanes and Cables

Low-Power High-Speed Short-Reach

Alternative to TIA/EIA-485

LOGIC DIAGRAM (POSITIVE LOGIC)

SN65MLVD080, SN65MLVD082

Channel 1

1DE

Cellular Base Stations

Central-Office Switches

Network Switches and Routers

DESCRIPTION

The SN65MLVD080 and SN65MLVD082 provide eight

half-duplex transceivers for transmitting and receiving

Multipoint-Low-Voltage Differential Signals in full

compliance with the TIA/EIA-899 (M-LVDS) standard,

which are optimized to operate at signaling rates up to 250

Mbps. The driver outputs have been designed to support

2DE − 8DE

2A − 8A

2B − 8B

2D − 8D

2R − 8R

Channels 2 − 8

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

(1)

The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

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12 3 4 5 6 7...24

中文翻译

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与SM65MLVD080DGGR相关器件

型号	品牌	获取价格	描述	数据表
SM65MLVD082DGGR	TI	获取价格	8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS
SM65MLVD128DGGR	TI	获取价格	1:8 LVTTL TO M-LVDS REPEATER DUAL 1:4 LVTTL TO M-LVDS REPEATER
SM65MLVD129DGGR	TI	获取价格	1:8 LVTTL TO M-LVDS REPEATER DUAL 1:4 LVTTL TO M-LVDS REPEATER
SM65MLVD202AD	TI	获取价格	MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SM65MLVD202ADR	TI	获取价格	LINE TRANSCEIVER, PDSO14, PLASTIC, SOIC-14
SM65MLVD203D	TI	获取价格	MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SM65MLVD203DR	TI	获取价格	IC,LINE TRANSCEIVER,BICMOS,1 DRIVER,1 RCVR,SOP,14PIN,PLASTIC
SM65MLVD205AD	TI	获取价格	MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SM65MLVD205ADR	TI	获取价格	LINE TRANSCEIVER, PDSO14, PLASTIC, SOIC-14
SM65MLVD207D	TI	获取价格	MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

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