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SM320C31GFAS60 PDF预览

SM320C31GFAS60

更新时间： 2024-11-20 03:31:39
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德州仪器 - TI 外围集成电路数字信号处理器时钟
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59页 1228K
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DIGITAL SIGNAL PROCESSORS

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SM320C31GFAS60 数据手册

 浏览型号SM320C31GFAS60的Datasheet PDF文件第2页浏览型号SM320C31GFAS60的Datasheet PDF文件第3页浏览型号SM320C31GFAS60的Datasheet PDF文件第4页浏览型号SM320C31GFAS60的Datasheet PDF文件第5页浏览型号SM320C31GFAS60的Datasheet PDF文件第6页浏览型号SM320C31GFAS60的Datasheet PDF文件第7页 
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SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
D
D
Processed to MIL-PRF-38535 (QML)  
D
D
Two Low-Power Modes  
Operating Temperature Ranges:  
− Military (M) −55°C to 125°C  
− Special (S) −55°C to 105°C  
On-Chip Memory-Mapped Peripherals:  
− One Serial Port Supporting  
8-/16-/24-/32-Bit Transfers  
− Two 32-Bit Timers  
D
D
SMD Approval  
− One-Channel Direct Memory Access  
(DMA) Coprocessor for Concurrent I/O  
and CPU Operation  
High-Performance Floating-Point Digital  
Signal Processor (DSP):  
− SMJ320C31-60 (5 V)  
D
Fabricated Using Enhanced Performance  
Implanted CMOS (EPIC) Technology by  
Texas Instruments (TI)  
33-ns Instruction Cycle Time  
330 Million Operations Per Second  
(MOPS), 60 Million Floating-Point  
Operations Per Second (MFLOPS),  
30 Million Instructions Per Second  
(MIPS)  
D
D
D
Two- and Three-Operand Instructions  
40 / 32-Bit Floating-Point /Integer Multiplier  
and Arithmetic Logic Unit (ALU)  
− SMJ320C31-50 (5 V)  
Parallel ALU and Multiplier Execution in a  
Single Cycle  
40-ns Instruction Cycle Time  
275 MOPS, 50 MFLOPS, 25 MIPS  
− SMJ320C31-40 (5 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
− SMJ320LC31-40 (3.3 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
− SMQ320LC31-40 (3.3 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
D
Block-Repeat Capability  
D
Zero-Overhead Loops With Single-Cycle  
Branches  
D
D
D
Conditional Calls and Returns  
Interlocked Instructions for  
Multiprocessing Support  
Bus-Control Registers Configure  
Strobe-Control Wait-State Generation  
D
Validated Ada Compiler  
D
D
D
D
D
D
D
D
32-Bit High-Performance CPU  
D
Integer, Floating-Point, and Logical  
Operations  
16-/32-Bit Integer and 32-/40-Bit  
Floating-Point Operations  
D
D
D
32-Bit Barrel Shifter  
32-Bit Instruction and Data Words, 24-Bit  
Addresses  
One 32-Bit Data Bus (24-Bit Address)  
Packaging  
Two 1K Word × 32-Bit Single-Cycle  
Dual-Access On-Chip RAM Blocks  
− 132-Lead Ceramic Quad Flatpack With  
Nonconductive Tie-Bar (HFG Suffix)  
− 141-Pin Ceramic Staggered Pin  
Grid- Array Package (GFA Suffix)  
− 132-Lead TAB Frame  
Boot-Program Loader  
64-Word × 32-Bit Instruction Cache  
Eight Extended-Precision Registers  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
− 132-Lead Plastic Quad Flatpack  
(PQ Suffix)  
description  
The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point  
processors manufactured in 0.6-µm triple-level-metal CMOS technology. The devices are part of the  
SMJ320C3x generation of DSPs from Texas Instruments.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 2006, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...59

中文翻译

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SM320C31GFAS60 替代型号

型号 品牌 替代类型 描述 数据表
SMJ320C31GFAS60 TI

完全替代

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