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SM2404T-10I PDF预览

SM2404T-10I

更新时间： 2024-01-30 00:09:59
品牌 Logo 应用领域
铁电 - RAMTRON 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 110K
描述
Cache DRAM, 1MX16, 6ns, CMOS, PDSO50, TSOP2-50

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SM2404T-10I 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：50
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.83
访问模式：DUAL BANK PAGE BURST最长访问时间：6 ns
其他特性：AUTO/SELF REFRESHJESD-30 代码：R-PDSO-G50
长度：20.95 mm内存密度：16777216 bit
内存集成电路类型：CACHE DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：50字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.2 mm自我刷新：YES
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

SM2404T-10I 数据手册

 浏览型号SM2404T-10I的Datasheet PDF文件第2页浏览型号SM2404T-10I的Datasheet PDF文件第3页浏览型号SM2404T-10I的Datasheet PDF文件第4页浏览型号SM2404T-10I的Datasheet PDF文件第5页浏览型号SM2404T-10I的Datasheet PDF文件第6页浏览型号SM2404T-10I的Datasheet PDF文件第7页 
Industrial Temperature  
16Mbit Enhanced Synchronous DRAM  
1Mx16 ESDRAM  
Preliminary Data Sheet  
Description  
Features  
As a JEDEC superset standard, the Enhanced Synchronous  
DRAM (ESDRAM) is an evolutionary modification to the  
JEDEC standard SDRAM. The industrial temperature grade  
version operates over an extended temperature range of -40°C  
to 85 °C. While completely compatible with standard  
SDRAM, ESDRAM incorporates changes that reduce  
latency, increase bandwidth, and allow concurrent operations  
to the same bank.  
•
•
Extended Temperature Range (-40°C to 85 °C)  
High Performance:  
CAS Latency = 2  
-7.5  
133  
7.5  
-10  
100  
10  
5
Units  
MHz  
ns  
fCK  
Clock Frequency  
tCK2 Clock cycle  
tAC2 Clock Access Time  
4.5  
ns  
•
•
•
•
•
•
•
JEDEC Superset Standard ESDRAM  
8Kbit SRAM Row Cache  
The 16Mbit ESDRAM combines a fast DRAM array with an  
8Kbit SRAM cache. The DRAM array is separated into two  
fully independent 8Mbit banks, with 4Kbits of SRAM cache  
per bank. The cache provides high-speed random column  
access, and with auto-precharge, allows operations to the  
DRAM array concurrent with cache reads. These operations  
include row activation, precharge, and refresh. Hidden row  
activation makes it possible to pipeline random row reads to  
reduce the page miss latency to that of a page hit.  
Supports Row Pipelining for Random Row Reads  
Programmable Burst length (1, 2, 4, 8, full page)  
Programmable CAS Latency (1, 2, 3)  
Automatic and Controlled Precharge Command  
Low Power Suspend, Self Refresh, and Power  
Down Modes Supported  
2K Refresh / 64 ms  
Single 3.3V ± 0.3V Power Supply  
LVTTL and 2.5V I/O Interface with Flexible VDDQ  
50-pin TSOP-II (0.8mm pin pitch)  
•
•
•
•
This device supports Self Refresh mode and operates with a  
single 3.3V ± 0.3V power supply. It is available in a 400mil  
TSOP Type II package.  
1Mx16 ESDRAM Block Diagram  
Bank A  
8Mbit  
Bank B  
8Mbit  
A(11:0)  
Sense Amplifiers  
Sense Amplifiers  
CLK  
SRAM Row Cache  
Column Decoder  
SRAM Row Cache  
Column Decoder  
CKE  
Command  
/CS  
Decoder  
/RAS  
and  
Timing  
/CAS  
/WE  
Generator  
UDQM  
Data I/O Buffers  
DQ  
LDQM  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.0  
Page 1 of 9  
1234567...9

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与SM2404T-10I相关器件

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