Datasheet > SM2405T-6

SM2405T-6

更新时间： 2024-01-28 18:58:10

品牌	Logo	应用领域
铁电 - RAMTRON		时钟动态存储器内存集成电路
页数	文件大小	规格书
99页	2618K
描述
Cache DRAM, 512KX32, 4.2ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

SM2405T-6 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP, QFP100,.63X.87	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.92
访问模式：	DUAL BANK PAGE BURST	最长访问时间：	4.2 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	166 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	16777216 bit
内存集成电路类型：	CACHE DRAM	内存宽度：	32
功能数量：	1	端口数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
刷新周期：	2048	座面最大高度：	1.6 mm
自我刷新：	YES	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.002 A	子类别：	Other Memory ICs
最大压摆率：	0.34 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

SM2405T-6 数据手册

0316409C 4M

412/10, 3.3V, SR. 0316169C 1M x 1612/8, 3.3V, SR. 0316809C 2M x 812/9, 3.3V, SR.

512Kx32

Preliminary Data Sheet

16Mbit Enhanced Synchronous DRAM

Overview

Features

• High Performance:

CAS latency = 2

• Programmable Burst Length: 1,2,4,8,full-page

-6

166

-7.5

133

7.5

-10

100

Units

MHz

• Programmable Wrap Sequence, Sequential or

Interleaved

f_CK

t_CK2

t_AC2

Clock Frequency

Clock Cycle

• Automatic and Controlled Precharge Command

• Hidden Precharge and Hidden Auto Refresh

• Self Refresh

Clock Access Time

4.2

4.5

• 8Kbit SRAM Row Cache per Bank

• Supports Row Pipelining for Random Row

• Suspend Mode and Power Down Mode

• 2048 refresh cycles / 32ms

Reads of 4:1:1:1:2:1:1:1:2:1:1:1 @ 133MHz

• Pin Compatible with JEDEC Standard SGRAMs

• Single 3.3V ± 0.3V Power Supply

• JEDEC Superset Standard ESDRAM

• Programmable Caching Policy

• LVTTL and 2.5V I/O Interface with Flexible V_DDQ

• Package: 100 pin LQFP (0.65 mm pin pitch)

• Programmable CAS Latency: 1, 2, 3

• Dual Banks controlled by A10 (Bank Select)

Description

the user to perform operations on the DRAM array

concurrent with cache reads. These operations

include new row activation, precharge, and refresh-

ing the DRAM array. Since new row activations can

occur during cache read cycles, it is possible for the

ESDRAM to pipeline random row reads, thus reduc-

ing the page miss latency to that of a page hit.

As a JEDEC superset standard, the Enhanced Syn-

chronous DRAM is an evolutionary modification to a

JEDEC standard Synchronous DRAM. The

ESDRAM incorporates changes to a standard

SDRAM which reduce the latency, increase the

bandwidth, and allow for concurrent operations to

the same bank. Even with these improvements in

performance and functionality, the Enhanced

SDRAM remains pin compatible with a JEDEC stan-

dard 512Kx32 SGRAM. As a result, this ESDRAM is

plug-compatible with an SGRAM and operates like a

standard SDRAM when used in an SDRAM applica-

tion.

This device is designed to comply with all JEDEC

standards set for SDRAM products, both electrically

and mechanically. All the control, address, and data

input/output circuits are synchronized with the posi-

tive edge of an externally supplied clock.

Prior to any access operation, the CAS latency,

burst length, burst sequence, and write caching pol-

icy must be programmed into the device by address

inputs A0-A10 during a Mode Register Set com-

mand cycle. The write policy is set as either Write

Transfer mode or No Write Transfer mode.

The 512Kx32 Enhanced Synchronous DRAM com-

bines a fast DRAM array with a 16Kbit SRAM cache.

The DRAM array is separated into two fully indepen-

dent 8Mbit DRAM banks with 8Kbits of SRAM cache

per bank. The SRAM cache is integrated into the

DRAM array as tightly coupled row registers. The

integrated cache provides several advantages. The

first advantage is high speed random column

accesses (<10ns). Another advantage is that

through the use of auto-precharge, the cache allows

This device supports Self Refresh mode, and oper-

ates with a single 3.3V ± 0.3V power supply. The

device is available in a 100 pin LQFP package.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com

The information contained herein is subject to change without notice.

Revision 1.0

Page 1 of 99

12 3 4 5 6 7...99

下载PDF

与SM2405T-6相关器件

型号	品牌	描述	获取价格	数据表
SM240A	TAYCHIPST	SURFACE MOUNT SCHOTTKY BARRIER RECTIFIERS	获取价格
SM240A	UNIOHM	2.0 AMP SURFACE MOUNT SCHOTTKY BARRIER RECTIFIERS	获取价格
SM240A	SECOS	2.0 AMP Surface Mount Schottky Barrier Rectifiers	获取价格
SM240A	LRC	Schottky Barrier Rectifiers Reverse Voltage 20 to100V	获取价格
SM240A-E	LRC	Schottky Barrier Rectifiers Reverse Voltage 20 to100V Forward Current 2.0A	获取价格
SM240AF	SECOS	20V ~200V 2.0 Amp Surface Mount Schottky Barrier Rectifiers	获取价格

与SM2405T-6相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

SM2405T-6

SM2405T-6 技术参数

SM2405T-6 数据手册

与SM2405T-6相关器件

与SM2405T-6相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SM2405T-6

SM2405T-6 技术参数

SM2405T-6 数据手册

与SM2405T-6相关器件

与SM2405T-6相关文章

您还可以找

您在本页遇到什么问题？