Datasheet > SM2404T-7.5

SM2404T-7.5

更新时间： 2024-01-22 00:41:22

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟光电二极管
页数	文件大小	规格书
100页	1871K
描述
Memory IC, 1MX16, CMOS, PDSO50,

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技术参数
数据手册

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SM2404T-7.5 技术参数

生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	SOP,	针数：	50
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.75
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PDSO-G50
内存密度：	67108864 bit	内存集成电路类型：	CACHE DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	50
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	自我刷新：	YES
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子位置：	DUAL
Base Number Matches：	1

SM2404T-7.5 数据手册

0316409C 4M

x 412/10, 3.3V, SR. 0316169C 1M x 1612/8, 3.3V, SR. 0316809C 2M x 812/9, 3.3V, SR.

4Mx4, 2Mx8, 1Mx16

Preliminary Data Sheet

16Mbit Enhanced Synchronous DRAM

Overview

Features

• High Performance:

CAS latency = 2

• Programmable Burst Length: 1,2,4,8,full-page

-6.6 -7.5

-10

100

Units

MHz

• Programmable Wrap Sequence, Sequential or

Interleaved

f_CK

t_CK2

t_AC2

Clock Frequency

Clock Cycle

150

6.6

4.3

133

7.5

4.5

• Automatic and Controlled Precharge Command

• Hidden Precharge and Hidden Auto Refresh

• Self Refresh

Clock Access Time

• 8Kbit SRAM Row Cache

• Supports Row Pipelining for Random Row

• Suspend Mode and Power Down Mode

• 2048 refresh cycles / 64ms

Reads of 4:1:1:1:2:1:1:1:2:1:1:1 @ 133MHz

• Compatible with JEDEC Standard SDRAMs

• Single 3.3V Power Supply

• JEDEC Superset Standard ESDRAM

• Programmable Caching Policy

• LVTTL and 2.5V I/O Interface with Flexible V_DDQ

• Package: 44 pin 400 mil TSOP-Type II (x4,x8)

50 pin 400 mil TSOP-Type II (x16)

• Programmable CAS Latency: 1, 2, 3

• Dual Banks controlled by A11 (Bank Select)

Description

to perform operations on the DRAM array concur-

rent with cache reads. These operations include

new row activation, precharge, and refreshing the

DRAM array. Since new row activations can occur

during cache read cycles, it is possible for the

ESDRAM to pipeline random row reads, thus reduc-

ing the page miss latency to that of a page hit.

As a JEDEC superset standard, the Enhanced Syn-

chronous DRAM is an evolutionary modification to a

JEDEC standard 16Mbit Synchronous DRAM. The

ESDRAM incorporates changes to a standard

SDRAM which reduce the latency, increase the

bandwidth, and allow for concurrent operations to

the same bank. Even with these improvements in

performance and functionality, the Enhanced

SDRAM remains pin and command compatible with

a JEDEC standard 16Mbit SDRAM. As a result, the

ESDRAM is plug-compatible with an SDRAM and

operates like a standard SDRAM when used in an

SDRAM application.

This device is designed to comply with all JEDEC

standards set for SDRAM products, both electrically

and mechanically. All the control, address, and data

input/output circuits are synchronized with the posi-

tive edge of an externally supplied clock.

Prior to any access operation, the CAS latency,

burst length, burst sequence, and write caching pol-

icy must be programmed into the device by address

inputs A0-A11 during a Mode Register Set com-

mand cycle. The write policy is set as either Write

Transfer mode or No Write Transfer mode.

The 16Mbit Enhanced Synchronous DRAM com-

bines a fast DRAM array with an 8Kbit SRAM cache.

The DRAM array is separated into two fully indepen-

dent 8Mbit DRAM banks with 4Kbits of SRAM cache

per bank. The SRAM cache is integrated into the

DRAM array as tightly coupled row registers. The

integrated cache provides several advantages. The

first advantage is high speed random column

accesses (10ns). Another advantage is that through

the use of auto-precharge, the cache allows the user

This device supports Self Refresh mode and oper-

ates with a single 3.3V power supply. The device is

available in a 400mil TSOP Type II package.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com

The information contained herein is subject to change without notice.

Revision 2.1

Page 1 of 100

12 3 4 5 6 7...100

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与SM2404T-7.5相关器件

型号	品牌	描述	获取价格	数据表
SM2404T-7.5I	RAMTRON	Cache DRAM, 4MX16, 5.4ns, CMOS, PDSO50, TSOP2-50	获取价格
SM2405Q-10	RAMTRON	Cache DRAM, 512KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, LQFP-100	获取价格
SM2405Q-6	RAMTRON	Cache DRAM, 512KX32, 4.2ns, CMOS, PQFP100, QFP-100	获取价格
SM2405Q-6.6	RAMTRON	Cache DRAM, 512KX32, 4.3ns, CMOS, PQFP100, 14 X 20 MM, LQFP-100	获取价格
SM2405Q-7.5	RAMTRON	Cache DRAM, 512KX32, 4.5ns, CMOS, PQFP100, 14 X 20 MM, LQFP-100	获取价格
SM2405T-10	RAMTRON	Cache DRAM, 512KX32, 5ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100	获取价格

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