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SM2403T-6 PDF预览

SM2403T-6

更新时间: 2024-01-24 06:51:23
品牌 Logo 应用领域
铁电 - RAMTRON 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 90K
描述
Cache DRAM, 2MX8, 4.3ns, CMOS, PDSO44, TSOP2-44

SM2403T-6 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP, TSOP44,.46,32针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.83
访问模式:DUAL BANK PAGE BURST最长访问时间:4.3 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):166 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
内存密度:16777216 bit内存集成电路类型:CACHE DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:44
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5/3.3,3.3 V
认证状态:Not Qualified刷新周期:2048
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.002 A子类别:Other Memory ICs
最大压摆率:0.28 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

SM2403T-6 数据手册

 浏览型号SM2403T-6的Datasheet PDF文件第2页浏览型号SM2403T-6的Datasheet PDF文件第3页浏览型号SM2403T-6的Datasheet PDF文件第4页浏览型号SM2403T-6的Datasheet PDF文件第5页浏览型号SM2403T-6的Datasheet PDF文件第6页浏览型号SM2403T-6的Datasheet PDF文件第7页 
16Mbit Enhanced SDRAM Family  
4Mx4, 2Mx8, 1Mx16  
Preliminary  
Features  
·
100% Pin, Function, and Timing Compatible with  
JEDEC standard SDRAM  
·
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Hidden Auto-Refresh without closing Read Pages  
Low Power Suspend, Self-Refresh, and Power Down Modes  
Optional No Write Transfer Mode  
·
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Integrated 8Kbit SRAM Row Cache  
Synchronous Operation up to 166MHz  
22ns Row Access Latency, 10ns Column Latency  
Early Auto-Precharge  
Programmable Burst Length (1, 2, 4, 8, full page)  
Programmable CAS Latency (1, 2, 3)  
Single 3.3V ± 0.3V Power Supply  
Flexible VDDQ Supports LVTTL and 2.5V I/O  
Packages: 44-pin TSOP-II (400 mils wide)  
50-pin TSOP-II (400 mils wide)  
The two bank architecture combines 22ns DRAM arrays  
with a 10ns SRAM row cache per bank. The ESDRAM is a  
superset technology of JEDEC standard SDRAM. Its two  
key functional features include early auto-precharge (close  
DRAM page while burst reads are performed) and an  
optional No Write Transfer mode. The ESDRAM is capable  
of maintaining two open read pages and two open write  
pages simultaneously via the No Write Transfer mode.  
Description  
The Enhanced Memory Systems 16Mb enhanced  
SDRAM (ESDRAM) family combines raw speed with  
innovative architecture to optimize system price-  
performance in high performance computer and  
embedded control systems.  
The ESDRAM is pin compatible with JEDEC standard  
SDRAM. It is also function and timing compatible with  
JEDEC standard SDRAM.  
FUNCTIONAL BLOCK DIAGRAM  
BANK A  
BANK B  
8Mbit  
A(11:0)  
8Mbit  
SENSE AMPLIFIERS  
SENSE AMPLIFIERS  
SRAM ROW CACHE  
COLUMN DECODER  
SRAM ROW CACHE  
COLUMN DECODER  
CLK  
CKE  
/CS  
COMMAND  
DECODER  
and  
/RAS  
Product  
4Mx4  
Cache Size  
1Kx4  
DQ  
/CAS  
/WE  
TIMING  
GENERATOR  
DQM(1:0)  
2Mx8  
512x8  
1Mx16  
256x16  
The information contained herein is subject to change without notice.  
Enhanced reserves the right to change or discontinue this product  
without notice.  
Ó 1998 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO 80921  
Telephone (800) 545-DRAM, Fax (719) 488-9095, Web http://www.edram.com Rev. 2.2  

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