Datasheet > SLG7NT41021V

SLG7NT41021V

更新时间： 2024-02-28 23:19:28

品牌	Logo	应用领域
DIALOG		双倍数据速率
页数	文件大小	规格书
8页	218K
描述
DDR Sequencer and FET Driver

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中文翻译

获取价格

数据手册

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SLG7NT41021V 数据手册

SLG7NT41021

DDR Sequencer and FET Driver

General Description

Pin Configuration

Silego SLG7NT41021 is a low power and small

form device. The SoC is housed in a 2mm x 3mm

STQFN package which is optimal for using with

small devices.

Features

VDD

DDR_PMOS_Q1

DDR_PMOS_Q2

V12S_MON

• Low Power Consumption

• Pb-Free / RoHS Compliant

• Halogen-Free

VDDQ_PWRGD

SLP_S3_N

NFET_V5DUAL_USB_N

DDR_NMOS_Q3

• STQFN-20 Package

SUS_ACK_N

PS1

Output Summary

• 4 Outputs — Push Pull 1X

• 5 Outputs — Open Drain NMOS 1X

• 1 Output — 3-State 1X

SUS_WARN_N

GND

V5S_MON

PFET_V5DUAL_USB

STQFN-20

TOP VIEW

Silego Technology, Inc.

Rev 1.05

Revised April 20, 2016

SLG7NT41021_DS_r105

SLG7NT41021_GP_r006

12 3 4 5 6 7 8

中文翻译

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