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SI5344H-42H

更新时间： 2024-11-22 01:12:59
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
56页 1530K
描述
HIGH-FREQUENCY,

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SI5344H-42H 数据手册

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Si5344H/42H Rev D  
HIGH-FREQUENCY, ULTRA-LOW JITTER ATTENUATOR CLOCK  
WITH DIGITALLY-CONTROLLED OSCILLATOR  
Features  
High-speed outputs generate an  
ultra-low jitter output up to 2.75 GHz  
Up to four Multi-Synth outputs  
generate any frequency up to  
717.5 MHz  
Input frequency range:  
8 kHz to 750 MHz  
Maximum Output frequency:  
High-Frequency Mode: 2.75 GHz  
MultiSynth Mode: 717.5 MHz  
Jitter performance:  
Hitless input clock switching:  
automatic or manual  
Automatic free-run and holdover  
modes  
Glitchless on the fly output  
frequency changes  
Locks to gapped clock inputs  
DCO mode: as low as 0.001 ppb  
steps.  
Core voltage  
VDD: 1.8 V ±5%  
High Frequency Mode:  
<50 fs typ (1 MHz–40 MHz)  
MultiSynth Mode:  
VDDA: 3.3 V ±5%  
Ordering Information:  
Independent output supply pins:  
3.3 V, 2.5 V, or 1.8 V  
See Section 7.  
<150 fs typ (12 kHz–20 MHz)  
Programmable jitter attenuation  
bandwidth: 10 Hz to 4 kHz  
Highly configurable outputs  
compatible with LVDS, LVPECL,  
LVCMOS, CML, and HCSL with  
programmable voltage swing and  
common mode  
Serial interface: I2C or SPI  
In-circuit programmable with  
non-volatile OTP memory  
Pin Assignments  
ClockBuilder ProTM software  
Si5342H 44QFN  
Top View  
simplifies device configuration  
Si5342H: 2 input, 2 output, QFN44  
Si5344H, 2 input, 4 output, QFN44  
Temperature range: –40 to +85 °C  
Pb-free, RoHS-6 compliant  
LVPECL-only in High Frequency  
Mode  
Status monitoring (LOS, OOF, LOL)  
1
2
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
IN1  
IN1  
INTR  
VDD  
3
LOS1  
IN_SEL0  
4
LOS0  
X1  
XA  
5
VDDS  
LOS_XAXB  
LOL  
GND  
Pad  
6
XB  
Applications  
7
X2  
VDDS  
OUT1  
8
VDDA  
9
VDDA  
NC  
100G/200G/400G Optical  
Transceivers  
Wireless base-stations  
10  
11  
OUT1  
VDDO1  
NC  
Description  
This specialized jitter attenuating clock multiplier combines fourth-generation  
DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high  
data rate coherent optical transceiver design. Up to four outputs can be assigned  
to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase  
jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode  
any-frequency outputs when added frequency flexibility is required, such as  
clocking Forward Error Correction (FEC) while still delivering <150 fs-rms typical  
phase jitter (12 kHz-20 MHz). The Si5344H and Si5342H also feature DCO-  
control with as low as 0.001 ppb step control and locks to gapped clock inputs.  
Si5344H 44QFN  
Top View  
1
2
33  
IN1  
IN1  
INTR  
VDD  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
3
OUT2  
IN_SEL0  
4
OUT2  
XGND  
XA  
5
VDDO2  
LOS_XAXB  
LOL  
GND  
Pad  
These devices are programmable via  
a serial interface with in-circuit  
6
XB  
7
XGND  
VDDA  
programmable non-volatile memory (NVM) so that they always power up with a  
known frequency configuration. The loop filter is fully integrated on-chip  
eliminating the risk of potential noise coupling associated with discrete solutions.  
Programming the Si5342H/44H is made easy with Silicon Labs’ ClockBuilderPro  
software. Factory preprogrammed devices are also available.  
VDDS  
8
9
OUT1  
VDDA  
NC  
10  
11  
OUT1  
VDDO1  
NC  
Rev. 1.0 9/16  
Copyright © 2016 by Silicon Laboratories  
Si5344H/42H  
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