Datasheet > SI5345A-B03247-GMR

SI5345A-B03247-GMR

更新时间： 2024-11-22 06:41:35

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
60页	1365K
描述
Processor Specific Clock Generator,

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Si5345/44/42

10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER

ATTENUATOR/CLOCK MULTIPLIER

Features



Generates any combination of output

frequencies from any input frequency

Input frequency range:

Differential: 8 kHz to 750 MHz

LVCMOS: 8 kHz to 250 MHz

Output frequency range:

Differential: up to 712.5 MHz

LVCMOS: up to 250 MHz

Ultra-low jitter:

<100 fs typ (12 kHz–20 MHz)

Programmable jitter attenuation

bandwidth from 0.1 Hz to 4 kHz

Meets G.8262 EEC Opt 1, 2 (SyncE)

Highly configurable outputs compatible

with LVDS, LVPECL, LVCMOS, CML,

and HCSL with programmable signal

amplitude

Status monitoring (LOS, OOF, LOL)

Hitless input clock switching:

automatic or manual

Locks to gapped clock inputs

Automatic free-run and holdover

modes



Optional zero delay mode

Fastlock feature: 50 ms typ lock time

Glitchless on the fly output frequency

changes

DCO mode: as low as 0.001 ppb

steps.



Core voltage

V : 1.8 V ±5%

V



: 3.3 V ±5%

DDA



Independent output supply pins: 3.3 V,

2.5 V, or 1.8 V

Output-output skew: <100 ps



Serial interface: I C or SPI

Ordering Information:

In-circuit programmable with

non-volatile OTP memory

See section 8



ClockBuilder Pro software simplifies

Functional Block Diagram

device configuration



Si5345: 4 input, 10 output, 64 QFN

Si5344: 4 input, 4 output, 44 QFN

Si5342: 4 input, 2 output, 44 QFN

Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

XTAL



Si5345/44/42

IN_SEL

OSC

Device Selector Guide

÷FRAC

IN0

IN1

IN2

Grade

Si534xA

Si534xB

Si534xC

Si534xD

Max Output Frequency Frequency Synthesis Modes

712.5 MHz

350 MHz

712.5 MHz

350 MHz

Integer+Fractional

Integer

DSPLL

IN3/

FB_IN

Optional

External

Feedback

Integer

Applications

Multi

Synth

÷INT

OUT0

OUT1

OUT2



OTN Muxponders and Transponders  Carrier Ethernet switches

10/40/100G networking line cards

GbE/10GbE/100GbE Synchronous

Ethernet (ITU-T G.8262)



SONET/SDH Line Cards

Broadcast video

Test and measurement

ITU-T G.8262 (SyncE) Compliant

Multi

Synth

÷INT

Multi

Synth

Multi

Synth

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

Description

Multi

Synth

These jitter attenuating clock multipliers combine fourth-generation DSPLL and

MultiSynth™ technologies to enable any-frequency clock generation and jitter

attenuation for applications requiring the highest level of jitter performance. These

devices are programmable via a serial interface with in-circuit programmable non-

volatile memory (NVM) so they always power up with a known frequency configuration.

They support free-run, synchronous, and holdover modes of operation, and offer both

automatic and manual input clock switching. The loop filter is fully integrated on-chip,

eliminating the risk of noise coupling associated with discrete solutions. Further, the

jitter attenuation bandwidth is digitally programmable, providing jitter performance

optimization at the application level. Programming the Si5345/44/42 is easy with

Silicon Labs’ ClockBuilderPro software. Factory preprogrammed devices are also

available.

NVM

I²C/SPI

Control/

Status

Preliminary Rev. 0.95 3/15

Si5345/44/42

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4 5 6 7...60

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