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SI5330G-A00217-GM PDF预览

SI5330G-A00217-GM

更新时间: 2024-11-23 12:04:39
品牌 Logo 应用领域
芯科 - SILICON 时钟驱动器逻辑集成电路
页数 文件大小 规格书
20页 158K
描述
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

SI5330G-A00217-GM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC24,.16SQ,20
针数:24Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.56
Is Samacsys:N系列:CMOS
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N24
长度:4 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.004 A功能数量:1
反相输出次数:端子数量:24
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源:1.8/3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:0.9 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:4 mm最小 fmax:200 MHz
Base Number Matches:1

SI5330G-A00217-GM 数据手册

 浏览型号SI5330G-A00217-GM的Datasheet PDF文件第2页浏览型号SI5330G-A00217-GM的Datasheet PDF文件第3页浏览型号SI5330G-A00217-GM的Datasheet PDF文件第4页浏览型号SI5330G-A00217-GM的Datasheet PDF文件第5页浏览型号SI5330G-A00217-GM的Datasheet PDF文件第6页浏览型号SI5330G-A00217-GM的Datasheet PDF文件第7页 
Si5330  
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW  
CLOCK BUFFER/LEVEL TRANSLATOR  
Features  
Supports single-ended or  
Output-output skew: 100 ps  
Propagation delay: 2.5 ns typ  
differential input clock signals  
Generates four differential  
(LVPECL, LVDS, HCSL) or eight  
single-ended (CMOS, SSTL,  
HSTL) outputs  
Single core supply with excellent  
PSRR: 1.8, 2.5, or 3.3 V  
Output driver supply voltage  
independent of core supply: 1.5,  
1.8, 2.5, or 3.3 V  
Provides signal level translation  
Differential to single-ended  
Single-ended to differential  
Differential to differential  
Single-ended to single-ended  
Wide frequency range  
Loss of Signal (LOS) indicator  
Ordering Information:  
allows system clock monitoring  
See page 14.  
Output Enable (OEB) pin allows  
glitchless control of output clocks  
Low power: 10 mA typical core  
Pin Assignments  
LVPECL, LVDS: 5 to 710 MHz  
HCSL: 5 to 250 MHz  
SSTL, HSTL: 5 to 350 MHz  
CMOS: 5 to 200 MHz  
current  
Industrial temperature range:  
°
–40 to +85 C  
Small size: 24-lead, 4 x 4 mm  
24  
23  
22  
21  
20  
19  
Additive jitter: 150 fs RMS typ  
QFN  
CLK1A  
CLK1B  
VDDO1  
IN1  
IN2  
Applications  
IN3  
GND  
High Speed Clock Distribution  
Ethernet Switch/Router  
SONET / SDH  
PCI Express 2.0/3.0  
Fibre Channel  
MSAN/DSLAM/PON  
Telecom Line Cards  
RSVD_GND  
RSVD_GND  
VDDO2  
CLK2A  
RSVD_GND  
CLK2B  
7
8
9
10  
11  
12  
Functional Block Diagram  
VDD  
VDDO0  
CLK0  
Si5330  
VDDO1  
CLK1  
Single-ended  
Single-ended  
or  
Differential  
IN  
or  
VDDO2  
CLK2  
Differential  
VDDO3  
CLK3  
LOS  
Control  
OEB  
Rev. 1.0 4/12  
Copyright © 2012 by Silicon Laboratories  
Si5330  

SI5330G-A00217-GM 替代型号

型号 品牌 替代类型 描述 数据表
SI5330F-A00215-GM SILICON

完全替代

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR
SI5330F-A00214-GM SILICON

完全替代

Supports single-ended or differential input clock singnals Generates four differential (LV

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