Datasheet > SI50122-A5

SI50122-A5

更新时间： 2024-11-22 01:15:55

品牌	Logo	应用领域
芯科 - SILICON		PC 输出元件
页数	文件大小	规格书
14页	1196K
描述
CRYSTAL-LESS PCI-EXPRESS GEN 1, GEN 2, & GEN 3 DUAL OUTPUT CLOCK GENERATOR

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中文翻译

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数据手册

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SI50122-A5 数据手册

Si50122-A5/A6

CRYSTAL-LESS PCI-EXPRESS GEN 1, GEN 2, & GEN 3

DUAL OUTPUT CLOCK GENERATOR

Features

 Crystal-less clock generator with  Triangular spread spectrum

integrated CMEMS

profile for maximum EMI

reduction (Si50122-A6)

 PCI-Express Gen 1/2/3 compliant

 Two PCIe 100 MHz differential

 Industrial Temperature –40 to

HCSL outputs

85 °C

 One 25 MHz single-ended

 2.5 V, 3.3 V Power supply

LVCMOS output

 Small package 10-pin TDFN

 Supports Serial (ATA) at

(2.0x2.5 mm)

100 MHz

 Si50122-A5 does not support

Ordering Information:

 Low power differential output

spread spectrum outputs

See page 10

buffers

 Si50122-A6 supports 0.5% down

 No termination resistors required

spread outputs

for differential output clocks

Pin Assignments

Applications

VSS

REFOUT

VDD

 Network Attached Storage

 Multi-function Printer

 Digital TV

 Solid State Drives (SSD)

 Wireless Access Point

 Home Gateway

Si50122

DIFF2

 Set top box

 Digital Video Cameras

DIFF1

Description

DIFF1

VSS

Si50122-A5/A6 is a high performance, crystal-less PCIe clock generator

that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS

clock outputs. The clock outputs are compliant to PCIe Gen 1, Gen 2, and

Gen 3 specifications. The ultra-small footprint (2.0x2.5 mm) and industry-

leading low power consumption make Si50122-A5/A6 the ideal clock

solution for consumer and embedded applications where board space is

limited and low power is needed.

Patents pending

Functional Block Diagram

VDD

REFOUT

DIFF1

PLL

(SSC)

Divider

CMEMS

DIFF2

VSS

Rev 0.7 9/14

Si50122-A5/A6

12 3 4 5 6 7...14

中文翻译

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