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SI50122-A5-GMR PDF预览

SI50122-A5-GMR

更新时间: 2024-01-29 01:58:48
品牌 Logo 应用领域
芯科 - SILICON 时钟光电二极管外围集成电路
页数 文件大小 规格书
14页 1196K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, TDFN-10

SI50122-A5-GMR 技术参数

生命周期:Obsolete包装说明:TDFN-10
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
其他特性:CRYSTAL-LESS CLOCK GENERATOR; IT ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码:R-PDSO-G10
长度:2.5 mm端子数量:10
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:100 MHz封装主体材料:PLASTIC/EPOXY
封装代码:VSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH座面最大高度:0.95 mm
最大供电电压:2.75 V最小供电电压:2.25 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:2 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

SI50122-A5-GMR 数据手册

 浏览型号SI50122-A5-GMR的Datasheet PDF文件第2页浏览型号SI50122-A5-GMR的Datasheet PDF文件第3页浏览型号SI50122-A5-GMR的Datasheet PDF文件第4页浏览型号SI50122-A5-GMR的Datasheet PDF文件第5页浏览型号SI50122-A5-GMR的Datasheet PDF文件第6页浏览型号SI50122-A5-GMR的Datasheet PDF文件第7页 
Si50122-A5/A6  
CRYSTAL-LESS PCI-EXPRESS GEN 1, GEN 2, & GEN 3  
DUAL OUTPUT CLOCK GENERATOR  
Features  
Crystal-less clock generator with Triangular spread spectrum  
integrated CMEMS  
profile for maximum EMI  
reduction (Si50122-A6)  
PCI-Express Gen 1/2/3 compliant  
Two PCIe 100 MHz differential  
Industrial Temperature –40 to  
HCSL outputs  
85 °C  
One 25 MHz single-ended  
2.5 V, 3.3 V Power supply  
LVCMOS output  
Small package 10-pin TDFN  
Supports Serial (ATA) at  
(2.0x2.5 mm)  
100 MHz  
Si50122-A5 does not support  
Ordering Information:  
Low power differential output  
spread spectrum outputs  
See page 10  
buffers  
Si50122-A6 supports 0.5% down  
No termination resistors required  
spread outputs  
for differential output clocks  
Pin Assignments  
Applications  
VSS  
REFOUT  
NC  
1
2
3
4
5
10  
9
VDD  
VDD  
Network Attached Storage  
Multi-function Printer  
Digital TV  
Solid State Drives (SSD)  
Wireless Access Point  
Home Gateway  
8
Si50122  
DIFF2  
DIFF2  
Set top box  
Digital Video Cameras  
7
DIFF1  
Description  
6
DIFF1  
VSS  
Si50122-A5/A6 is a high performance, crystal-less PCIe clock generator  
that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS  
clock outputs. The clock outputs are compliant to PCIe Gen 1, Gen 2, and  
Gen 3 specifications. The ultra-small footprint (2.0x2.5 mm) and industry-  
leading low power consumption make Si50122-A5/A6 the ideal clock  
solution for consumer and embedded applications where board space is  
limited and low power is needed.  
Patents pending  
Functional Block Diagram  
VDD  
REFOUT  
DIFF1  
PLL  
(SSC)  
Divider  
CMEMS  
DIFF2  
VSS  
Rev 0.7 9/14  
Copyright © 2014 by Silicon Laboratories  
Si50122-A5/A6  

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