Si5013
OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amplifier:
ꢀ Supports OC-12/3, STM-4/1
ꢀ DSPLL® technology
ꢀ Loss-of-signal level alarm
ꢀ Data slicing level control
ꢀ 10 mV differential sensitivity
(typ)
ꢀ Jitter generation 2.3 mUI
PP
rms
ꢀ 3.3 V supply
ꢀ Small footprint: 5 x 5 mm
ꢀ Reference and reference-less
Ordering Information:
operation supported
See page 22.
Applications
ꢀ SONET/SDH/ATM routers
ꢀ Add/drop multiplexers
ꢀ Digital cross connects
ꢀ Board level serial links
ꢀ SONET/SDH test equipment
ꢀ Optical transceiver modules
ꢀ SONET/SDH regenerators
Pin Assignments
Si5013
Description
28 27 26 25 24 23 22
RATESEL
GND
VDD
21
1
2
3
4
5
6
7
The Si5013 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-12/3 and STM-4/1 rates. Use of an external reference
clock is optional. Silicon Laboratories DSPLL technology eliminates
sensitive noise entry points, thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
20 REXT
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
19 RESET/CAL
GND
Pad
18
17
16
15
VDD
DOUT+
DOUT–
TDI
®
8
9
10 11 12 13 14
The Si5013 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
LOS_LVL
Signal
Detect
DSQLCH
LOS
2
DOUT+
DOUT–
Retimer
BUF
BUF
2
DIN+
DIN–
Limiting
Amp
DSPLL
BER
Monitor
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
Reset/
Calibration
Bias Gen.
REXT
BER_ALM
RESET/CAL
RATESEL
BER_LVL
SLICE_LVL
LOL
LTR
Rev. 1.5 10/05
Copyright © 2005 by Silicon Laboratories
Si5013