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SI2414-BT PDF预览

SI2414-BT

更新时间: 2024-11-26 10:17:35
品牌 Logo 应用领域
芯科 - SILICON 光电二极管
页数 文件大小 规格书
74页 823K
描述
Modem, 14.4kbps Data, PDSO24, TSSOP-24

SI2414-BT 数据手册

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Si2456/33/14  
®
V.90, V.34, V.32BIS ISOMODEM CHIPSET WITH INTEGRATED GLOBAL DAA  
Features  
Data modem formats  
Integrated DAA  
ITU-T, Bell  
Over 5000 V capacitive isolation  
300 bps up to 56 kbps  
V.42, V.42bis, MNP2-5  
Automatic rate negotiation  
Parallel phone detect  
Globally-compliant line interface  
Overcurrent detection  
Caller ID decode  
3.3 V power  
No external ROM or RAM required  
UART with flow control  
AT command set support  
Fast connect  
Parallel interface  
Call progress support  
Firmware upgradeable  
Ordering Information  
This data sheet is valid only for  
those chipset combinations listed  
on page 69.  
Applications  
Set-top boxes  
E-mail terminals  
Point-of-sale terminals  
Digital video recorders  
Security systems  
Remote monitoring  
Pin Assignments  
Si2456/33/14  
Description  
24  
23  
22  
21  
CLKIN/XTALI  
EECLK/D5  
1
2
3
The Si2456 is a complete, ITU-V.90-compliant, 56 kbps modem chipset  
with integrated direct access arrangement (DAA) that provides a  
programmable line interface to meet global telephone line requirements  
with a single design. Available in two small packages, it eliminates the  
need for a separate DSP data pump, external RAM and ROM, modem  
controller, codec, isolation transformer, relays, opto-isolators, and 2- to 4-  
XTALO  
DCD/D4  
ESC/D3  
CLKOUT/EECS/A0  
D6  
VD3.3  
GND  
C1A  
4
5
ISOB  
VD3.3  
GND  
20  
19  
6
7
8
9
VDA  
18  
17  
®
RTS/D7  
VDB  
wire hybrid. The ISOmodem chipset is ideal for embedded modem  
16  
15  
14  
EESD/D2  
RI/D1  
RXD/RD  
applications due to its small board space, low power consumption, and  
global compliance. The Si2433 and Si2414 products offer all the same  
features as the Si2456 with connect rates of up to 33.6 kbps and  
14.4 kbps, respectively.  
10  
11  
12  
TXD/WR  
CTS/CS  
INT/D0  
AOUT/INT  
13  
RESET  
Functional Block Diagram  
Si3015  
1
2
3
4
QE2  
DCT  
IGND  
C1B  
16  
15  
FILT2  
FILT  
CLKIN/XTALI  
CLKOUT  
XTALO  
RX  
14  
13  
PLL  
Clocking  
REXT  
REXT2  
RAM/ROM  
Data Bus  
RNG1  
RNG2  
12  
11  
5
6
7
RXD  
TXD  
CTS  
RTS  
DCD  
ESC  
RI  
REF  
QB  
QE  
10  
9
VREG2  
VREG  
Serial  
Interface  
8
C1A  
DAA  
Interface  
Microcontroller  
DSP  
To Phone  
Line  
INT  
Patents pending  
AOUT  
ISOB  
CS  
WR  
RD  
Parallel  
Interface  
A0  
D0-D7  
RESET  
Rev. 1.2 8/06  
Copyright © 2006 by Silicon Laboratories  
Si2456/33/14  

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