Si2457/34/15/04
®
V.90, V.34, V.32BIS, V.22BIS ISOMODEM WITH GLOBAL DAA
Features
This data sheet applies to Si2457/34/ Integrated DAA
15/04 Revision D
Data modem formats
Over 6000 V capacitive
isolation
Parallel phone detect
Globally-compliant line
interface
ITU-T, Bell
300 bps up to 56 kbps
V.21,V.22, V.29 Fast Connect
V.44, V.42, V.42bis, MNP2-5
Automatic rate negotiation
Type I and II caller ID decode
No external ROM or RAM required
UART, SPI, or parallel interface
Flexible clock options
Low-cost 32.768 kHz oscillator
4.915 MHz oscillator
Overcurrent detection
AT command set support
SMS / MMS support
Firmware upgradeable
EEPROM interface
Lead-free, RoHS-compliant
packages
Ordering Information
This data sheet is valid only for
those chipset combinations listed
on page 50.
Commercial or industrial
temperature range
27 MHz clock input
Pin Assignments
DTMF detection/generation
Applications
Si2457/34/15/04
(16-Pin Option)
Set-top boxes
Point-of-sale terminals
Text / video telephones
Digital video recorder
Digital televisions
Remote monitoring
CLKIN/XTALI
XTALO
1
2
3
4
16 SS/RTS
15 DCD
RI
VD
ESC
14
13 VA
MISO/RXD
MOSI/TXD
SCLK/CTS
RESET
5
6
7
8
GND
12
11
Description
INT
10
9
C1A
C2A
The ISOmodem® family of products is a complete modem ranging in speed
from 56,000 bps to 2400 bps. Offered as a chipset with the Si2457, Si2434,
Si2415, or Si2404 system-side device and the Si3018/10 line-side device,
the ISOmodem utilizes Silicon Laboratories’ patented direct access
arrangement (DAA) technology to provide a programmable telephone line
interface with an unparalleled level of integration. These compact solutions
eliminate the need for a separate DSP, modem controller, codec,
transformer, relay, opto-isolators, clocking crystal, and 2-4 wire hybrid.
Available with a system-side packaging option of either a 16-pin SOIC or a
24-pin TSSOP, these devices are ideal for embedded modem applications
due to their flexibility, small footprint, and minimal external component
count.
Si2457/34/15/04
(24-Pin Option)
CLKIN/XTALI
XTALO
24
23
22
1
2
3
4
5
6
7
8
SDO/EECLK/D5
DCD/D4
CLKOUT/EECS/A0
FSYNC/D6
VD3.3
ESC/D3
21
VD3.3
20 GND
19
18
VDB
GND
VDA
SDI/EESD/D2
SS/RTS/D7
17 RI/D1
16
15 AOUT/INT
INT/DO
MISO/RXD/RD
MOSI/TXD/WR
9
10
14
13
C1A
C2A
SCLK/CTS/CS 11
RESET 12
System Block Diagram
Si3018/10
QE
DCT2
1
2
3
4
16
DCT
15
IGND
DCT3
QB
RX
IB
14
13
Si24xx
System
Side
Si3018
Line
Side
Global
DAA
BOM
Tip
Ring
Host
CPU
Host Interface
Telco
C1B
C2B
QE2
5
6
7
12
11
SC
VREG
RNG1
10
9
VREG2
RNG2
8
UART
SPI
Parallel
Capacitive
Isolation Barrier
Rev. 1.3 12/10
Copyright © 2010 by Silicon Laboratories
Si2457/34/15/04