120V Boot, 4A Peak, High Frequency
High-side and Low-side Driver
SGM48211
APPLICATION INFORMATION
The SGM48211 implements both the level-shifting and
buffer-drive functions to boost the 3.3V signal to the
gate-drive voltage to fully turn on the power device for
achieving high-frequency switching, minimizing noise
and controlling floating power-device gates and
reducing power losses.
example, when the SGM48211 is used to drive an
IPB60R120P7 power MOSFET with a DC bus voltage
of 400V in a continuous conduction mode (CCM) PFC
converter, the turn-on event and the turn-off event are
supposed to be completed in approximately 14ns and
8ns (refer to DS of IPB60R120P7 with typical 36nC of
total QG) separately. Therefore, a source current of
2.57A (= 36nC/14ns) and a sink current of 4.5A (=
36nC/8ns) or higher are necessary. The SGM48211
can provide 4A peak source current and sink currents
larger than the requirements of IPB60R120P7.
The SGM48211 is designed with low propagation
delays and adopts low-inductance and compact
package. It is available to drive wide band-gap power
device such as GaN based switches for supporting very
high switching frequency and low-cost component
count.
In practical designs, the parasitic inductance of PCB
traces will limit the di/dt of the gate driving current that
may not reach the full peak current capability of the
driver. To minimize this impact caused by the parasitic
inductance, it is recommended to place the gate drive
device as close to the power MOSFET as possible and
design a tight gate driving loop with minimum parasitic
inductance.
Design Requirements
Table 3. Design Specifications
Design Parameter
Supply Voltage, VDD
Voltage on HS, VHS
Voltage on HB, VHB
Output Current Rating, IO
Operating Frequency
Example Value
12V
0V to 100V
12V to 112V
-4A to 4A
500kHz
External gate resistors for turn-on and turn-off of the
MOSFETs should be chosen carefully to achieve
efficiency and EMI optimizations.
Input Threshold Type
Propagation Delay
The SGM48211 can handle a maximum input voltage
range from -10V to 20V to achieve enhanced
robustness and allow compatibility with both inputs
from microcontrollers, as well as higher-voltage inputs
from gate-drive transformers. The inputs adopt TTL and
CMOS compatible structure with a wide range of
hysteresis. The voltage threshold is independent of
VDD.
The SGM48211 features 31ns (TYP) propagation delay
and 3ns (TYP) delay matching between the high-side
and the low-side drivers, which make it possible for the
device to operate in very high frequency with little pulse
distortion.
Power Dissipation
Power dissipation is the sum of conduction loss and
switching loss as shown in Equation 1.
Supply Voltage VDD
The SGM48211 operates with a wide supply voltage
range from 8V to 17V for applications such as driving Si
MOSFETs, IGBTs, SiC MOSFETs and GaN FETs. The
maximum voltage on VDD when applied to a
single-ended power, and the differential voltage of the
positive voltage and the negative voltage when applied
to dual-railed power, as well as the bias supply voltage
on the VDD pin should never exceed the values listed
in the Absolute Maximum Ratings section.
PDISS = PDC + PSW
(1)
where PDC is the conduction loss and can be calculated
by Equation 2.
PDC = IQ × VDD
(2)
where
IQ is the total quiescent current consumed by all internal
block circuits and internal parasitic devices during
switching (such as charging and discharging).
VDD is the voltage between the VDD and VSS pins.
Peak Driving Currents
The SGM48211 is designed with 4A peak source and
sink currents for fast switching of power devices. For
SG Micro Corp
www.sg-micro.com
DECEMBER 2023
13
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