Datasheet > SCP600-27MSC

SCP600-27MSC

更新时间： 2024-11-20 09:32:23

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
4页	192K
描述
Dual XO with 4 CMOS Outputs 10MHz to 52MHz

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数据手册

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SCP600-27MSC 数据手册

Preliminary PLL600-27M

Dual XO with 4 CMOS Outputs 10MHz to 52MHz

FEATURES

PIN ASSIGNMENT

•

Generates 4 CMOS outputs from 2 crystal inputs

• XIN1- Accepts a 10 to 52MHz crystal input

and generates 1 CMOS output at the same

frequency.

• XIN2- Accepts a 10 to 52MHz crystal input

and generates 3 CMOS outputs at the same

frequency.

Low phase noise (-130 dBc @ 10kHz offset).

Low jitter (RMS): 2.5ps period jitter.

12mA drive capability at TTL output.

1.62V to 3.63V DC operation.

XIN1

GND

XOUT1

N/C

GND

VDD

•

CLK2A

VDD

CLK1

GND

Available in 14 pin 150mil SOIC.

CLK2B

XOUT2

CLK2C

XIN2

DESCRIPTION

The PLL600-27M is part of PhaseLink ’s low cost

family of XO IC’s, designed to replace multiple XO

solutions saving the cost and board space of clock

distribution buffers. In addition, this product family

provides among the lowest current on the market for

the 10MHz to 52MHz range. They accept input

crystals from 10MHz to 52MHz (fundamental

resonant mode) and provide low phase noise (<-

130dBc at 10kHz offset at 30MHz), and very low

jitter (2.5 ps RMS period jitter) outputs.

BLOCK DIAGRAM

XIN1

XOUT1

XTAL

OSC

CLK1

CLK2A

CLK2B

CLK2C

XTAL

OSC

XIN2

XOUT2

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 1

12 3 4

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