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SCANPSC100F

更新时间： 2024-02-19 02:51:16

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		控制器
页数	文件大小	规格书
21页	209K
描述
Embedded Boundary Scan Controller (IEEE 1149.1 Support)

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技术参数
数据手册

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SCANPSC100F 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.62
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e3
长度：	17.9 mm	湿度敏感等级：	3
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	2.65 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANPSC100F 数据手册

Parallel Processor Interface (PPI) (Continued)

TIMING WAVEFORMS (Continued)

FIGURE 4. Consecutive Read/Writes (best case timing)

FIGURE 5. Consecutive Read/Writes (worst case timing)

Note 3: Figures 4, 5: Figure 4 shows the best case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe

occurs a setup time, t_S4or before the falling edge of SCK. This allows the cycle to be completed within 1.5 clock SCK clock cycles. Figure 5 shows the worst

case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe does not meet the t_S4requirement between STB

and SCK. Therefore, the propagation of the internal PSC100 control and reset signals is delayed until the next falling edge of SCK. The bus cycle is then

completed 1.5 SCK cycles later creating a total bus cycle time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing, t_S4is not a manda-

tory timing specification.

FIGURE 6. Read/Write or Write/Read (best case timing)

FIGURE 7. Read/Write or Write/Read (worst case timing)

Note 4: Figures 6, 7: This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write data/address

latches and control logic allow consecutive read/write or write/read operations to be overlapped (i.e., do not need to wait 2 or 3 SCK cycles between bus

cycles). For the best case timing scenario (Figure 6: rising edge of STB to falling edge of SCK greater than t_S4), a new bus cycle can be performed each SCK

cycle. For the worst timing scenario (Figure 7: rising edge of STB to falling edge of SCK is less than t_S4), a one SCK cycle delay must be included after each

back to back read/write or write/read sequence.

Note 5: Figures 4, 5, 6, 7 assume that the PSC100 register participating in the bus cycle is ready to accept/provide data. For bus cycles involving a PSC100

shifter/buffer(s), the ready status of a shifter/buffer can be checked using the status bits in Mode Register 2 prior to the start of the bus cycle. Polling is

required when the RDY pin is not used to provide a processor “handshake”.

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与SCANPSC100F相关器件

型号	品牌	描述	获取价格	数据表
SCANPSC100FFMQB	FAIRCHILD	Microprocessor Circuit, CMOS, CDFP28, CERPACK-28	获取价格
SCANPSC100FMW	TI	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, SOIC-28	获取价格
SCANPSC100FSC	FAIRCHILD	Embedded Boundary Scan Controller (IEEE 1149.1 Support)	获取价格
SCANPSC100FSC	ROCHESTER	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 0.300 INCH, MS-013, SOIC-28	获取价格
SCANPSC100FSCX	ROCHESTER	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 0.300 INCH, MS-013, SOIC-28	获取价格
SCANPSC110	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格

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