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SCANPSC100F PDF预览

SCANPSC100F

更新时间: 2024-01-22 00:19:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 控制器
页数 文件大小 规格书
21页 209K
描述
Embedded Boundary Scan Controller (IEEE 1149.1 Support)

SCANPSC100F 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknown风险等级:5.62
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:17.9 mm湿度敏感等级:3
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

SCANPSC100F 数据手册

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December 1991  
Revised May 2000  
SCANPSC100F  
Embedded Boundary Scan Controller  
(IEEE 1149.1 Support)  
General Description  
Features  
Compatible with IEEE Std. 1149.1 (JTAG) Test Access  
The SCANPSC100F is designed to interface a generic par-  
allel processor bus to a serial scan test bus. It is useful in  
improving scan throughput when applying serial vectors to  
system test circuitry and reduces the software overhead  
that is associated with applying serial patterns with a paral-  
lel processor. The SCANPSC100F operates by serializing  
data from the parallel bus for shifting through the chain of  
1149.1 compliant components (i.e., scan chain). Scan data  
returning from the scan chain is placed on the parallel port  
to be read by the host processor. Up to two scan chains  
can be directly controlled with the SCANPSC100F via two  
independent TMS pins. Scan control is supplied with user  
specific patterns which makes the SCANPSC100F proto-  
col-independent. Overflow and underflow conditions are  
prevented by stopping the test clock. A 32-bit counter is  
used to program the number of TCK cycles required to  
complete a scan operation within the boundary scan chain  
or to complete a SCANPSC100F Built-In Self Test (BIST)  
operation. SCANPSC100F device drivers and 1149.1  
embedded test application code are available with Fair-  
child’s SCAN Ease software tools.  
Port and Boundary Scan Architecture  
Supported by Fairchild’s SCAN Ease (Embedded Appli-  
cation Software Enabler) Software  
Uses generic, asynchronous processor interface; com-  
patible with a wide range of processors and PCLK fre-  
quencies  
Directly supports up to two 1149.1 scan chains  
16-bit Serial Signature Compaction (SSC) at the Test  
Data In (TDI) port  
Automatically produces pseudo-random patterns at the  
Test Data Out (TDO) port  
Fabricated on FACT 1.5 µm CMOS process  
Supports 1149.1 test clock (TCK) frequencies up to  
25 MHz  
TTL-compatible inputs; full-swing CMOS outputs with  
24 mA source/sink capability  
Ordering Code:  
Order Number  
Package Number  
Package Description  
SCANPSC100FSC  
M28B  
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010968  
www.fairchildsemi.com  

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