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SCAN921821TSM PDF预览

SCAN921821TSM

更新时间: 2024-11-21 21:04:59
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动接口集成电路驱动器
页数 文件大小 规格书
11页 621K
描述
IC DUAL LINE DRIVER, PBGA100, FBGA-100, Line Driver or Receiver

SCAN921821TSM 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:FBGA-100Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.5差分输出:YES
驱动器位数:2输入特性:STANDARD
接口集成电路类型:LINE DRIVER接口标准:IEEE 1149.1
JESD-30 代码:S-PBGA-B100JESD-609代码:e0
长度:10 mm湿度敏感等级:3
功能数量:2端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA100,10X10,32封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):235
电源:3.3 V认证状态:Not Qualified
最大接收延迟:座面最大高度:1.5 mm
子类别:Line Driver or Receivers最大压摆率:325 mA
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

SCAN921821TSM 数据手册

 浏览型号SCAN921821TSM的Datasheet PDF文件第2页浏览型号SCAN921821TSM的Datasheet PDF文件第3页浏览型号SCAN921821TSM的Datasheet PDF文件第4页浏览型号SCAN921821TSM的Datasheet PDF文件第5页浏览型号SCAN921821TSM的Datasheet PDF文件第6页浏览型号SCAN921821TSM的Datasheet PDF文件第7页 
November 2004  
SCAN921821  
Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1  
(JTAG), and At-Speed BIST  
General Description  
Features  
n 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps total  
throughput  
The SCAN921821 is a dual channel 18-bit serializer featur-  
ing signal conditioning, boundary SCAN, and at-speed BIST.  
Each serializer block transforms an 18-bit parallel LVCMOS/  
LVTTL data bus into a single Bus LVDS data stream with  
embedded clock. This single serial data stream with embed-  
ded clock simplifies PCB design and reduces PCB cost by  
narrowing data paths that in turn reduce PCB size and  
layers. The single serial data stream also reduces cable  
size, the number of connectors, and eliminates clock-to-data  
and data-to-data skew.  
n 8-level selectable pre-emphasis on each channel drives  
lossy cables and backplanes  
>
n
15kV HBM ESD protection on Bus LVDS I/O pins  
n Robust BLVDS serial data transmission with embedded  
clock for exceptional noise immunity and low EMI  
n Power saving control pin for each channel  
n IEEE 1149.1 "JTAG" Compliant  
n At-Speed BIST - PRBS generation  
n No external coding required  
n Internal PLL, no external PLL components required  
n Single +3.3V power supply  
n Low power: 260 mW (typ) per channel at 66 MHz with  
PRBS-15 pattern  
Each channel also has an 8-level selectable pre-emphasis  
feature that significantly extends performance over lossy  
interconnect. Each channel also has its own powerdown pin  
that saves power by reducing supply current when the chan-  
nel is not being used.  
The SCAN921821 also incorporates advanced testability  
features including IEEE 1149.1 and at-speed BIST PRBS  
pattern generation to facilitate verification of board and link  
integrity  
n Single 3.3 V supply  
n Fabricated with advanced CMOS process technology  
n Industrial −40 to +85˚C temperature range  
n Compact 100-ball FBGA package  
Block Diagram  
20084401  
© 2004 National Semiconductor Corporation  
DS200844  
www.national.com  

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