5秒后页面跳转
捷配首页

Datasheet > SCAN92LV090SLC
SCAN92LV090SLC PDF预览

SCAN92LV090SLC

更新时间： 2024-11-22 11:12:55
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路驱动器
页数 文件大小 规格书
22页 881K
描述
具有边界扫描功能的 9 通道总线 LVDS 收发器 | NZC | 64 | -40 to 85

阅读下载

中文翻译

获取价格

SCAN92LV090SLC 技术参数

生命周期：Not Recommended零件包装代码：BGA
包装说明：BGA-64针数：64
Reach Compliance Code：not_compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.42Is Samacsys：N
差分输出：YES驱动器位数：9
高电平输入电流最大值：0.00002 A输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE TRANSCEIVER接口标准：IEEE 1149.1
JESD-30 代码：S-PBGA-B64JESD-609代码：e0
长度：8 mm湿度敏感等级：3
功能数量：9端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE最大输出低电流：0.002 A
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA64,8X8,32
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：235电源：3.3 V
认证状态：Not Qualified最大接收延迟：3.9 ns
接收器位数：9座面最大高度：1.5 mm
子类别：Line Driver or Receivers最大压摆率：210 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：2.6 ns宽度：8 mm
Base Number Matches：1

SCAN92LV090SLC 数据手册

 浏览型号SCAN92LV090SLC的Datasheet PDF文件第2页浏览型号SCAN92LV090SLC的Datasheet PDF文件第3页浏览型号SCAN92LV090SLC的Datasheet PDF文件第4页浏览型号SCAN92LV090SLC的Datasheet PDF文件第5页浏览型号SCAN92LV090SLC的Datasheet PDF文件第6页浏览型号SCAN92LV090SLC的Datasheet PDF文件第7页 
SCAN92LV090  
www.ti.com  
SNLS058I –SEPTEMBER 2000–REVISED APRIL 2013  
SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN  
Check for Samples: SCAN92LV090  
1
FEATURES  
DESCRIPTION  
The SCAN92LV090A is one in a series of Bus LVDS  
transceivers designed specifically for the high speed,  
low power proprietary backplane or cable interfaces.  
The device operates from a single 3.3V power supply  
and includes nine differential line drivers and nine  
receivers. To minimize bus loading, the driver outputs  
and receiver inputs are internally connected. The  
separate I/O of the logic side allows for loop back  
support. The device also features a flow through pin  
out which allows easy PCB routing for short stubs  
between its pins and the connector.  
2
•
•
•
•
IEEE 1149.1 (JTAG) Compliant  
Bus LVDS Signaling  
Low Power CMOS Design  
High Signaling Rate Capability (Above 100  
Mbps)  
•
0.1V to 2.3V Common Mode Range for VID  
200mV  
=
•
•
±100 mV Receiver Sensitivity  
Supports Open and Terminated Failsafe on  
Port Pins  
The driver translates 3V TTL levels (single-ended) to  
differential Bus LVDS (BLVDS) output levels. This  
allows for high speed operation, while consuming  
minimal power with reduced EMI. In addition, the  
differential signaling provides common mode noise  
rejection of ±1V.  
•
•
3.3V Operation  
Glitch Free Power Up/Down (Driver & Receiver  
Disabled)  
•
Light Bus Loading (5 pF Typical) per Bus  
LVDS Load  
The receiver threshold is less than ±100 mV over a  
±1V common mode range and translates the  
differential Bus LVDS to standard (TTL/CMOS)  
levels.  
•
•
•
Designed for Double Termination Applications  
Balanced Output Impedance  
Product Offered in 64 Pin LQFP Package and  
NFBGA Package  
This device is compliant with IEEE 1149.1 Standard  
Test Access Port and Boundary Scan Architecture  
with the incorporation of the defined boundary-scan  
test logic and test access port consisting of Test Data  
Input (TDI), Test Data Out (TDO), Test Mode Select  
(TMS), Test Clock (TCK), and the optional Test Reset  
(TRST).  
•
High Impedance Bus Pins on Power Off (VCC  
0V)  
=
SIMPLIFIED FUNCTIONAL DIAGRAM  
D0+/RI+  
BLVDS I/O  
D0-/RI-  
D
D
IN  
DE  
R
R
OUT  
RE  
Channel 1 of 9  
Common to all  
data channels  
TDI  
TDO  
IEEE 1149.1 (JTAG)  
Test Access Port  
TCK  
TMS  
TRST  
Figure 1.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2013, Texas Instruments Incorporated  
1234567...22

中文翻译

下载PDF

SCAN92LV090SLC 替代型号

型号 品牌 替代类型 描述 数据表
SCAN92LV090SLC/NOPB TI

类似代替

 具有边界扫描功能的 9 通道总线 LVDS 收发器 | NZC | 64 | -40 to
SCAN92LV090SLC NSC

功能相似

 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

与SCAN92LV090SLC相关器件

型号 品牌 获取价格 描述 数据表
SCAN92LV090SLC/NOPB TI

获取价格

 		具有边界扫描功能的 9 通道总线 LVDS 收发器 | NZC | 64 | -40 to
SCAN92LV090SLCX/NOPB TI

获取价格

 		9 LINE TRANSCEIVER, PBGA64, BGA-64
SCAN92LV090VEH NSC

获取价格

 		9 Channel Bus LVDS Transceiver w/ Boundary SCAN
SCAN92LV090VEH/NOPB NSC

获取价格

 		IC 9 LINE TRANSCEIVER, PQFP64, LQFP-64, Line Driver or Receiver
SCAN92LV090VEH/NOPB TI

获取价格

 		具有边界扫描功能的 9 通道总线 LVDS 收发器 | PM | 64 | -40 to
SCAN92LV090VEHX TI

获取价格

 		IC 9 LINE TRANSCEIVER, PQFP64, LQFP-64, Line Driver or Receiver
SCAN92LV090VEHX NSC

获取价格

 		IC 9 LINE TRANSCEIVER, PQFP64, LQFP-64, Line Driver or Receiver
SCAN92LV090VEHX/NOPB NSC

获取价格

 		IC 9 LINE TRANSCEIVER, PQFP64, LQFP-64, Line Driver or Receiver
SCANH162512ASM/NOPB TI

获取价格

 		SCAN/JTAG/3J SERIES, DUAL 8-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PBGA64, BGA-64
SCANH162512ASMX TI

获取价格

 		SCAN/JTAG/3J SERIES, DUAL 8-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PBGA64, BGA-64

与SCAN92LV090SLC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证