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SC68C752BIB48,128

更新时间： 2024-11-08 15:50:43
品牌 Logo 应用领域
恩智浦 - NXP 通信时钟数据传输先进先出芯片外围集成电路
页数 文件大小 规格书
48页 340K
描述
SC68C752B - 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode uP interfac QFP 48-Pin

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SC68C752BIB48,128 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP, QFP48,.35SQ,20
针数：48Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.73
其他特性：ALSO OPERATES AT 2.5V OR 5V SUPPLY地址总线宽度：4
边界扫描：NO最大时钟频率：80 MHz
通信协议：ASYNC, BIT最大数据传输速率：0.625 MBps
外部数据总线宽度：8JESD-30 代码：S-PQFP-G48
JESD-609代码：e3长度：7 mm
低功率模式：YES湿度敏感等级：1
串行 I/O 数：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Serial IO/Communication Controllers
最大供电电压：3.63 V最小供电电压：2.97 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

SC68C752BIB48,128 数据手册

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SC68C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte  
FIFOs and 68 mode μP interface  
Rev. 04 — 20 January 2010  
Product data sheet  
1. General description  
The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with  
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s.  
The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR)  
that stores receiver FIFO threshold levels to start/stop transmission during hardware and  
software flow control. With the FIFO Rdy register, the software gets the status of  
TXRDYn/RXRDYn for all four ports in one access. On-chip status registers provide the  
user with error indications, operational status, and modem interface control. System  
interrupts may be tailored to meet user requirements. An internal loopback capability  
allows on-board diagnostics.  
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TXn signal and  
receives characters on the RXn signal. Characters can be programmed to be 5 bits, 6 bits,  
7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be  
programmed to interrupt at different trigger levels. The UART generates its own desired  
baud rate based upon a programmable divisor and its input clock. It can transmit even,  
odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing  
errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The  
UART also contains a software interface for modem control operations, and has software  
flow control and hardware flow control capabilities.  
The SC68C752B is available in LQFP48 and HVQFN32 packages.  
2. Features  
„ Dual channel with 68 mode (Motorola) μP interface  
„ Up to 5 Mbit/s data rate  
„ 64-byte transmit FIFO  
„ 64-byte receive FIFO with error flags  
„ Programmable and selectable transmit and receive FIFO trigger levels for DMA and  
interrupt generation  
„ Software/hardware flow control  
‹ Programmable Xon/Xoff characters  
‹ Programmable auto-RTS and auto-CTS  
„ Optional data flow resume by Xon any character  
„ DMA signalling capability for both received and transmitted data  
„ Supports 5 V, 3.3 V and 2.5 V operation  
 
 
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SC68C752BIB48,128 替代型号

型号 品牌 替代类型 描述 数据表
SC68C752BIB48 NXP

完全替代

 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max

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