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SC68C94C1N PDF预览

SC68C94C1N

更新时间: 2024-11-07 22:22:19
品牌 Logo 应用领域
恩智浦 - NXP 微控制器和处理器串行IO控制器通信控制器外围集成电路光电二极管发射机接收机数据传输时钟
页数 文件大小 规格书
33页 213K
描述
nullQuad universal asynchronous receiver/transmitter QUART

SC68C94C1N 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-48针数:48
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.82Is Samacsys:N
地址总线宽度:6边界扫描:NO
最大时钟频率:8 MHz通信协议:ASYNC, BIT
数据编码/解码方法:NRZ最大数据传输速率:0.125 MBps
外部数据总线宽度:8JESD-30 代码:R-PDIP-T48
长度:62.1 mm低功率模式:YES
DMA 通道数量:I/O 线路数量:16
串行 I/O 数:4端子数量:48
片上数据RAM宽度:最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP48,.6
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V认证状态:Not Qualified
RAM(字数):0座面最大高度:4.9 mm
子类别:Serial IO/Communication Controllers最大压摆率:50 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:15.24 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

SC68C94C1N 数据手册

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Philips Semiconductors  
Product specification  
Quad universal asynchronous receiver/transmitter (QUART)  
SC68C94  
DESCRIPTION  
PIN CONFIGURATIONS  
The 68C94 quad universal asynchronous receiver/transmitter  
(QUART) combines four enhanced Philips Semiconductors  
industry-standard UARTs with an innovative interrupt scheme that  
can vastly minimize host processor overhead. It is implemented  
using Philips Semiconductors’ high-speed CMOS process that  
combines small die size and cost with low power consumption.  
V
CC  
A5:0  
CEN  
DACKN  
IACKN  
RDN  
WRN  
D7-0  
The operating speed of each receiver and transmitter can be  
selected independently at one of eighteen fixed baud rates, a 16X  
clock derived from a programmable counter/timer, or an external 1X  
or 16X clock. The baud rate generator and counter/timer can  
operate directly from a crystal or from external clock inputs. The  
ability to independently program the operating speed of the receiver  
and transmitter make the QUART particularly attractive for  
dual-speed channel applications such as clustered terminal  
systems.  
RQN  
RESET  
X1/CLK  
I/O0a–d  
I/O1a–d  
I/O2a–d  
X2  
I/O3a–d  
TDa-d  
RDa-d  
Each receiver is buffered with eight character FIFOs (first-in-first-out  
memories) and one shift register to minimize the potential for  
receiver overrun and to reduce interrupt overhead in interrupt driven  
systems. In addition, a handshaking capability is provided to disable  
a remote UART transmitter when the receiver buffer is full. (RTS  
control)  
V
SD00178  
SS  
Programmable channel mode  
Normal (full-duplex), automatic echo, local loop back, remote  
The 68C94 provides a power-down mode in which the oscillator is  
stopped and the register contents are stored. This results in reduced  
power consumption on the order of several magnitudes. The  
QUART is fully TTL compatible and operates from a single +5V  
power supply.  
loopback  
Programmable interrupt priorities  
Identification of highest priority interrupt  
Global interrupt register set provides data from interrupting  
channel  
FEATURES  
Vectored interrupts with programmable vector format  
IACKN and DTACKN signals  
New low overhead interrupt control  
Four Philips Semiconductors industry-standard UARTs  
Built-in baud rate generator with choice of 18 rates  
Four I/O pins per UART for modem controls, clocks, etc.  
Power down mode  
Eight byte receive FIFO and eight byte transmit FIFO for each  
UART  
Programmable data format:  
5 to 8 data bits plus parity  
High-speed CMOS technology  
Odd, even, no parity or force parity  
1, 1.5 or 2 stop bits programmable in 1/16-bit increments  
52-pin PLCC and 48-pin DIP  
Commercial and industrial temperature ranges available  
On-chip crystal oscillator  
Baud rate for the receiver and transmitter selectable from:  
23 fixed rates: 50 to 230.4K baud Non-standard rates to 1.0M  
baud  
TTL compatible  
User-defined rates from the programmable counter/timer  
Single +5V power supply with low power mode  
Two multifunction programmable 16-bit counter/timers  
1MHz 16x mode operation  
associated with each of two blocks  
External 1x or 16x clock  
Parity, framing, and overrun error detection  
False start bit detection  
30ns data bus release time  
“Watch Dog” timer for each receiver  
Line break detection and generation  
ORDERING INFORMATION  
COMMERCIAL  
= +5V +10%,  
INDUSTRIAL  
V = +5V +10%,  
CC  
PACKAGES  
DWG #  
V
T
CC  
o
o
o
o
= 0 C to +70 C  
T
= –40 C to +85 C  
SC68C94A1N  
SC68C94A1A  
A
A
48-Pin Plastic Dual In-Line Package (DIP)  
52-Pin Plastic Leaded Chip Carrier (PLCC)  
SC68C94C1N  
SC68C94C1A  
SOT240-1  
SOT238-3  
1
1995 May 1  
853-1601 15179  

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