Datasheet > S6E1A11B0A

S6E1A11B0A

更新时间： 2024-11-06 00:52:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器
页数	文件大小	规格书
95页	1828K
描述
32-Bit ARMÂ® CortexÂ® FM0 based Microcontroller

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S6E1A11B0A 数据手册

S6E1A11B0A/C0A

S6E1A12B0A/C0A

32-Bit ARM^®Cortex^®

FM0+ based Microcontroller

The S6E1A1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power

consumption and low cost.

This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such

as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN).

The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL

MANUAL".

Features

CSIO

 Full duplex double buffer

32-bit ARM Cortex-M0+ Core

 Built-in dedicated baud rate generator

 Overrun error detection function

 Serial chip select function (ch.1 and ch.3 only)

 Data length: 5 to 16 bits

Processor version: r0p1

Maximum operating frequency: 40 MHz

Nested Vectored Interrupt Controller (NVIC): 1 NMI

(non-maskable interrupt) and 32 peripheral interrupt with 4

selectable interrupt priority levels

LIN

 LIN protocol Rev.2.1 supported

 Full duplex double buffer

 Master/Slave mode supported

24-bit System timer (Sys Tick): System timer for OS task

management

 LIN break field generation function (The length is variable

between 13 bits and 16 bits.)

Bit Band operation

Compatible with Cortex-M3 bit band operation

 LIN break delimiter generation function (The length is

variable between 1 bit and 4 bits.)

 Various error detection functions available (parity errors,

framing errors, and overrun errors)

On-Chip Memories

Flash memory

 Up to 88 Kbyte

I²C

 Standard-mode (Max: 100 kbps) supported / Fast-mode

(Max 400kbps) supported.

 Read cycle:0 wait-cycle

 Security function for code protection

DMA Controller (2 channels)

The DMA Controller has its own bus independent of the CPU,

SRAM

The on-chip SRAM of this series has one independent SRAM.

and CPU and DMA Controller can process simultaneously.

 SRAM: 6 Kbyte

2 independently configurable and operable channels

Multi-function Serial Interface (Max 3channels)

It can start a transfer with a software request or a request

from a built-in peripheral.

128 bytes with FIFO in all channels (The number of FIFO

steps varies depending on the settings of the communication

mode or bit length.)

Transfer address area: 32 bits (4 Gbyte)

Transfer mode: block transfer/burst transfer/demand transfer

Transfer data type: byte/halfword/word

Transfer block count: 1 to 16

The operation mode of each channel can be selected from

one of the following.

 UART

 CSIO

 LIN

Number of transfers: 1 to 65536

 I²C

UART

 Full duplex double buffer

 Parity can be enabled or disabled.

 Built-in dedicated baud rate generator

 External clock available as a serial clock

Various error detection functions (parity errors, framing errors,

and overrun errors)

Cypress Semiconductor Corporation

Document Number: 002-05091 Rev.*A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 10, 2016

12 3 4 5 6 7...95

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与S6E1A11B0A相关器件

型号	品牌	获取价格	描述	数据表
S6E1A11B0AGN2	CYPRESS	获取价格	32-Bit ARMÂ® CortexÂ® FM0 based Microcontroll
S6E1A11B0AGN20000	CYPRESS	获取价格	32-bit ARMÂ® CortexÂ®-M0FM0 Microcontroller
S6E1A11B0AGN2000G	INFINEON	获取价格	FM0+ S6E1A-Series Arm® Cortex®-M0+ Microcontr
S6E1A11B0AGN2B000	CYPRESS	获取价格	32-bit ARMÂ® CortexÂ®-M0FM0 Microcontroller
S6E1A11B0AGN2B000	INFINEON	获取价格	FM0+ S6E1A-Series Arm® Cortex®-M0+ Microcontr
S6E1A11B0AGP2	CYPRESS	获取价格	32-bit Microcontroller FM0 Family
S6E1A11B0AGP20000	CYPRESS	获取价格	32-bit ARMÂ® CortexÂ®-M0FM0 Microcontroller
S6E1A11B0AGP20000	INFINEON	获取价格	FM0+ S6E1A-Series Arm® Cortex®-M0+ Microcontr
S6E1A11B0AGP2B000	INFINEON	获取价格	FM0+ S6E1A-Series Arm® Cortex®-M0+ Microcontr
S6E1A11C0AGF2	CYPRESS	获取价格	32-bit Microcontroller FM0 Family

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