5秒后页面跳转
S40032LK8MK7TW-75A PDF预览

S40032LK8MK7TW-75A

更新时间: 2024-10-27 22:22:51
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
9页 362K
描述
SYVCHRONOUS DRAM

S40032LK8MK7TW-75A 数据手册

 浏览型号S40032LK8MK7TW-75A的Datasheet PDF文件第1页浏览型号S40032LK8MK7TW-75A的Datasheet PDF文件第2页浏览型号S40032LK8MK7TW-75A的Datasheet PDF文件第3页浏览型号S40032LK8MK7TW-75A的Datasheet PDF文件第5页浏览型号S40032LK8MK7TW-75A的Datasheet PDF文件第6页浏览型号S40032LK8MK7TW-75A的Datasheet PDF文件第7页 
128Mb: x4, x8, x16  
SDRAM 3.3V  
AC ELECTRICAL CHARACTERISTICS: Vdd = 3.3V ± 10%V, Temp. = 25° to 70°C  
AC CHARACTERISTICS  
PARAMETER  
Access time from CLK (positive edge) CL = 3  
Access time from CLK (positive edge) CL = 2  
Address hold time  
Address setup time  
CLK high level width  
CLK low level width  
Clock cycle time CL = 3  
Clock cycle time CL = 2  
CKE hold time  
CKE setup time  
CS#, RAS#, CAS#, WE#, DQM hold time  
CS#, RAS#, CAS#, WE#, DQM setup time  
Data-in hold time  
-75A  
MIN  
-75A  
MAX  
5.4  
-8A  
MIN  
-8A  
MAX  
6
SYMBOL  
tAC  
UNITS  
ns  
NOTES  
tAC  
tAH  
tAS  
tCH  
tCL  
tCK  
tCK  
tCKH  
tCKS  
tCMH  
tCMS  
tDH  
N/A  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0.8  
1.5  
2.5  
2.5  
7.5  
N/A  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
1
2
3
3
10  
1
2
1
2
1
2
Data-in setup time  
tDS  
ns  
Data-out high impedance time  
Data-out low impedance time  
Data-out hold time  
ACTIVE to PRECHARGE command period  
AUTO REFRESH to ACTIVE command period  
ACTIVE to READ or WRITE delay  
Refresh period (4096 cycles)  
PRECHARGE command period  
ACTIVE bank A to bank B command period  
Transition time  
tHZ  
tLZ  
tOH  
tRAS  
tRC  
tRCD  
tREF  
tRP  
tRRD  
tT  
tWR  
tXSR  
tCCD  
tCKED  
tPED  
9
16K  
64  
2
9
16K  
64  
2
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
tCK  
tCK  
tCK  
tCK  
4
1
2.7  
44  
60  
22.5  
2
3
50  
80  
30  
22.5  
15  
0.3  
20  
8
1
1
1
30  
20  
0.3  
20  
8
1
1
1
Write recovery time  
3
Exit SELF REFRESH to ACTIVE command  
READ/WRITE command to READ/WRITE command  
CKE to clock disable or power down entry mode  
CKE to clock enable or power down exit setup  
1
2
2
AC ELECTRICAL CHARACTERISTICS: Vdd = 3.3V ± 10%V, Temp. = 25° to 70°C  
AC CHARACTERISTICS  
-75A  
-75A  
-8  
-8  
PARAMETER  
DQM to input data delay  
WRITE command to input data delay  
Data-in to ACTIVATE command w/ Auto precharge  
Data-in to precharge  
SYMBOL  
tDQD  
tDWD  
tDAL  
MIN  
MAX  
MIN  
MAX  
UNITS  
tCK  
tCK  
tCK  
tCK  
NOTES  
0
0
5
2
0
0
5
2
1
1
3
tDPL  
2, 3  
Last data-in to precharge command  
LOAD MODE REGISTER command to command  
Data-out to high impedance from precharge  
tRDL  
tMRD  
tROH  
2
2
3
2
2
3
tCK  
tCK  
tCK  
1
1
1
NOTES:  
1. Clocks required specified by JEDEC functionality and not dependent on any timing parameter.  
2. Timing actually specified by tCKS, clock(s) specified as a reference only at a minimum cycle rate.  
3. Timing actually specified by tWR plus tRP clock(s) specified as a reference only at a minimum cycle rate.  
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. The last valid data  
element will meet tOH before going high-Z.  
5. Based on tCK = 10ns for –8 and tCK = 7.5ns for –75a  
PDF: 09005aef807827f6 / Source: 09005aef807825bd  
128Mb SDRAM  
Rev: 11/29/2004  
SpecTek reserves the right to change products or  
specifications without notice. Ó 2001, 2002, 2004 SpecTek  
4
www.spectek.com  

与S40032LK8MK7TW-75A相关器件

型号 品牌 获取价格 描述 数据表
S40032LK8MK7TW-8A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK8FB-75A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK8FB-8A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK8FC-75A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK8FC-8A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK8TW-75A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK8TW-8A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK9FB-75A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK9FB-8A ETC

获取价格

SYVCHRONOUS DRAM
S40032LK8MK9FC-75A ETC

获取价格

SYVCHRONOUS DRAM