SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to TSCLK.
Although the frequency of PICLK and the internally
generated byte clock is the same, their phase rela-
tionship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
generated byte clock. Should the magnitude of the
phase difference be less than one bit period, and if
the SYNC input is high, the timing block inverts the
internal byte clock.
S3006 RECEIVER FUNCTIONAL
DESCRIPTION
The S3006 SERI receiver chip provides the first
stage of digital processing of a receive SONET STS-
12, STS-3, or ITU-T E4 bit serial stream. It converts
the bit-serial 622.08, 155.52, or 139.264 Mbit/s data
stream into 78 Mbyte/s, 19 Mbyte/s, or 17 Mbyte/s
byte-serial data format depending on the control set-
tings and reference frequency provided by the user.
A Coded Mark Inversion (CMI) decoder can be en-
abled during 155.52 Mbit/s and 139.264 Mbit/s
operation for decoding STS-3 electrical and E4 sig-
nals. These modes are selected by three input pins.
Clock recovery is performed on the incoming
scrambled NRZ or CMI–coded data stream. A refer-
ence clock is required for phase locked loop start-up
and proper operation under loss of signal conditions.
An integral prescaler and phase locked loop circuit is
used to multiply this reference frequency to the
nominal bit rate. Reference frequencies of 19.44
MHz, 38.88 MHz, 51.84 MHz, or 77.76 MHz are se-
lectable for SONET/SDH by the two reference select
input pins. In E4 applications, these same pins can
select the reference frequency from 17.408 MHz,
34.816 MHz, 46.421 MHz, or 69.632 MHz. For appli-
cations that provide a high-frequency bit clock
externally, the internal synthesizer may be by-
passed. (See Other Operating Modes.)
Since the inversion of the internal byte clock will cor-
rupt one byte of data, SYNC should be held low
except when a phase correction is desired. When a
timing domain phase difference of less than one bit
period is detected, the Phase Alignment Event out-
put (PAE) pulses high for one PCLK clock period. If
the condition persists, PAE will remain high. When
PAE conditions occur, SYNC should be activated un-
til the condition is no longer present.
The Timing Generator also produces a feedback ref-
erence clock to the Clock Synthesizer (BYTCLKIP).
A counter divides the synthesized clock down to the
same frequency as the reference clock REFCLK.
The PLL in the Clock Synthesizer maintains the sta-
bility of the synthesized clock by comparing the
phase of the BYTCLKIP clock with that of the refer-
ence clock (REFCLK). The modulus of the counter is
a function of the reference clock frequency and the
operating frequency.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver). Signal pins are provided to
allow for line loopback (receiver to transmitter) when
used with the compatible S3005 device.
Clock Recovery
Parallel-to-Serial Converter
The Clock Recovery function, as shown in the block
diagram in Figure 5, generates a clock that is fre-
quency matched to the incoming data baud rate at
the RSD or DLD differential inputs. The clock is
phase aligned by a PLL so that it samples the data
in the center of the data eye pattern.
The Parallel-to-Serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared
by a phase/frequency discriminator. Output pulses
from the discriminator indicate the required direction
of phase corrections. These pulses are smoothed by
an integral loop filter. The output of the loop filter
controls the frequency of the Voltage Controlled Os-
cillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) to
which the PLL locks when data is lost.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in
the Timing Generator description, activates the par-
allel data transfer between registers. In STS-12 and
STS-3 NRZ modes, the serial data is shifted out of
the second register at the TSCLK rate. In STS–3
CMI and E4 CMI modes, the serial data shifts out at
the TSCLK/2 rate to the CMI encoder.
Applied Micro Circuits Corporation
6
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