Datasheet > S3006B-1

S3006B-1

更新时间： 2024-09-17 19:10:27

品牌	Logo	应用领域
AMCC		电信电信集成电路
页数	文件大小	规格书
4页	205K
描述
TRANSCEIVER, UUC, DIE

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技术参数
数据手册

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S3006B-1 技术参数

生命周期：	Obsolete	零件包装代码：	DIE
包装说明：	DIE,	Reach Compliance Code：	unknown
风险等级：	5.82	JESD-30 代码：	X-XUUC-N
负电源额定电压：	-4.5 V	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	DIE
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
认证状态：	Not Qualified	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	TRANSCEIVER
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子位置：	UPPER	Base Number Matches：	1

S3006B-1 数据手册

APPLICATION NOTE

E4 FRAMING

E4 FRAMING CIRCUIT DESIGN

The S3005/S3006 parts can be used to implement

serializer/deserializer CMI encode/decode and the

clock synthesis/recovery functions for the CCITT

PDH E4 standard. In E4 (CMI) mode, however, the

framing of the 8-bit data bus is not performed in the

logic of the S3006. This application note explains

how this logic can be designed in the adjacent con-

troller device. The logic functions and frequency of

operation will allow the function to be implemented in

a FPGA device or a CMOS ASIC.

added to look for 3 consecutive “correct” framing

patterns before declaring frame sync. In addition,

the frame detect logic should be monitored to verify

that correct framing sequences are being seen after

frame sync is achieved. If correct framing se-

quences are not detected then the frame search

logic should be enabled again.

The circuit as shown in Figure 1 consists of an input

logic, and the E4 frame pattern detect logic. The

timing of the circuit is done using the S3006 POCLK

which is operating at 17 MHz. Data is clocked into

the input register from the POUT data lines of the

S3006. The data is then routed to the 8:1 multiplex-

ers which select the eight possible byte alignments.

The frame register contains the data to be examined

for correct frame alignment by the E4 frame detect

logic. The frame detect logic detects all of the pos-

sible byte alignments of the E4 framing pattern.

When the FA pattern is detected, the multiplexer se-

lection is then “frozen” and the additional ØX pattern

is checked before declaring frame sync. The de-

tailed circuit design and timing diagrams are shown

in Figures 2 and 3.

Framing Pattern

The E4 Frame Detect block decodes the

111110100000 pattern for compliance to the E4

standard.

General Design

The S3006 parallel output data is sampled in each of

eight possible alignments until the correct framing

pattern and sequence is seen. When the correct

framing pattern is detected by the E4 frame detect

block the 8:1 multiplexer selection is “frozen” and the

correctly framed data will be presented in the frame

rors) in a single frame. Additional filter logic can be

Figure 1. E4 Framing Block Diagram

S3006

POUT

POCLK

15-Bit Input Register

Frame

Detect

Frame

Detect

MUX

Select

Logic

8:1 MX

8-Bit Data Register

Applied Micro Circuits Corporation

6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333

Page 1

12 3 4

中文翻译

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与S3006B-1相关器件

型号	品牌	获取价格	描述	数据表
S3006B6	AMCC	获取价格	Receiver, 1-Func, DIE
S3006B-6	AMCC	获取价格	TRANSCEIVER, UUC, DIE
S3006C1	AMCC	获取价格	ATM/SONET/SDH Receiver, 1-Func, CQFP68, 0.050 INCH PITCH, CERAMIC, LDCC-68
S3006C-1	AMCC	获取价格	TRANSCEIVER, CQFP68, CERAMIC, LDCC-68
S3006C6	AMCC	获取价格	ATM/SONET/SDH Receiver, 1-Func, CQFP68, 0.050 INCH PITCH, CERAMIC, LDCC-68
S3006C-6	AMCC	获取价格	TRANSCEIVER, CQFP68, CERAMIC, LDCC-68
S3006D	TOSHIBA	获取价格	MIXER DIODE,6DB NOISE FIGURE,9.4GHZ F(TEST),PIN
S3006D1	AMCC	获取价格	ATM/SONET/SDH Receiver, 1-Func, PQFP80, 0.025 INCH PITCH, HEAT SINK, PLASTIC, QFP-80
S3006D-1	AMCC	获取价格	TRANSCEIVER, PQFP80, HEAT SINK, PLASTIC, QFP-80
S3006D6	AMCC	获取价格	ATM/SONET/SDH Receiver, 1-Func, PQFP80, 0.025 INCH PITCH, HEAT SINK, PLASTIC, QFP-80

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