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S29WS256N0LBAW012

更新时间： 2024-01-01 13:26:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路闪存
页数 文件大小 规格书
79页 1777K
描述
Flash, 16MX16, 70ns, PBGA84, 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84

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S29WS256N0LBAW012 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA, BGA84,10X12,32针数：84
Reach Compliance Code：compliantECCN代码：3A991.B.1.A
HTS代码：8542.32.00.51风险等级：5.73
最长访问时间：70 ns其他特性：SYNCHRONOUS BURST MODE OPERATION POSSIBLE
启动块：BOTTOM/TOP命令用户界面：YES
通用闪存接口：YES数据轮询：YES
JESD-30 代码：R-PBGA-B84JESD-609代码：e1
长度：11.6 mm内存密度：268435456 bit
内存集成电路类型：FLASH内存宽度：16
湿度敏感等级：3功能数量：1
部门数/规模：8,254端子数量：84
字数：16777216 words字数代码：16000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-25 °C组织：16MX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA84,10X12,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.8 V
编程电压：1.8 V认证状态：Not Qualified
座面最大高度：1 mm部门规模：16K,64K
最大待机电流：0.000005 A子类别：Flash Memories
最大压摆率：0.054 mA最大供电电压 (Vsup)：1.95 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
切换位：YES类型：NOR TYPE
宽度：8 mmBase Number Matches：1

S29WS256N0LBAW012 数据手册

 浏览型号S29WS256N0LBAW012的Datasheet PDF文件第2页浏览型号S29WS256N0LBAW012的Datasheet PDF文件第3页浏览型号S29WS256N0LBAW012的Datasheet PDF文件第4页浏览型号S29WS256N0LBAW012的Datasheet PDF文件第5页浏览型号S29WS256N0LBAW012的Datasheet PDF文件第6页浏览型号S29WS256N0LBAW012的Datasheet PDF文件第7页 
S29WS256N  
S29WS128N  
256/128 Mbit (16/8 M x 16 bit), 1.8 V,  
Simultaneous Read/Write, Burst Flash  
This product family has been retired and is not recommended for designs. For new and current designs, the S29WS128P and  
S29WS256P supersede the S29WS128N and S29WS256N respectively. These are the factory-recommended migration paths.  
Please refer to the S29WS-P Family data sheet for specifications and ordering information.  
General Description  
The Spansion S29WS256/128 are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst mode Flash  
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate  
data and address pins. These products can operate up to 80 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for  
today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.  
Distinctive Characteristics  
Single 1.8 V read/program/erase (1.70–1.95 V)  
110 nm MirrorBit™ Technology  
Hardware (WP#) protection of top and bottom sectors  
Dual boot sector configuration (p and bottom)  
Offered Packages  
Simultaneous Read/Write operation with zero latency  
32-word Write Buffer  
WS256N/128N: 84-ball FGA (8 mm x 11.6 mm)  
Low VCC write inhibi
Sixteen-bank architecture consisting of 16/8 Mwords for WS256N/  
128N, respectively  
Persistent and Password methods of Advanced Sector Protection  
Four 16 Kword sectors at both top and bottom of memory array  
254/126 64 Kword sectors (WS256N/128N)  
Write operation status bits indicate program and erase operation  
completion  
Programmable linear (8/16/32) with or without wrap around and  
Suspend and Resume commands for Program and Erase  
continuous burst read modes  
operations  
Secured Silicon Sector region consisting of 128 words each for  
Unlk Bypass program command to reduce programming time  
factory and customer  
Synchronous or Asynchronous program operation, independent of  
20-year data retention (typical)  
burst control register settings  
Cycling Endurance: 100,000 cycles per sector (typical)  
RDY output indicates data available to system  
Command set compatible with JEDEC (42.4) standard  
ACC input pin to reduce factory programming time  
Support for Common Flash Interface (CFI)  
Performance Characteristics  
Read Access Times  
Current Consumption (typical values)  
Speed Option (MHz)  
Max. Synch. Latency, ns (t  
80  
80  
9
66  
80  
54  
80  
Continuous Burst Read @ 80 MHz  
Simultaneous Operation (asynchronous)  
Program (asynchronous)  
38 mA  
50 mA  
19 mA  
19 mA  
20 µA  
)
IACC  
Max. Synch. Burst Access, ns (t  
)
11.2  
80  
13.5  
80  
BACC  
Max. Asynch. Access Time, ns (t  
)
80  
20  
80  
13.5  
Erase (asynchronous)  
ACC  
Max. Asynch. Page Access Time, ns (t  
)
20  
20  
Standby Mode (asynchronous)  
PACC  
Max CE# Access Time, ns (t  
Max OE# Access Time, ns (t  
)
80  
80  
CE  
)
13.5  
13.5  
OE  
Typical Program & Erase Times  
Single Word Programming  
Effective Write Buffer Programming (V ) Per Word  
40 µs  
9.4 µs  
6 µs  
CC  
Effective Write Buffer Programming (V  
Sector Erase (16 Kword Sector)  
Sector Erase (64 Kword Sector)  
) Per Word  
ACC  
150 ms  
600 ms  
Cypress Semiconductor Corporation  
Document Number: 002-01825 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 08, 2016  
1234567...79

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