S29WS256N
S29WS128N
256/128 Mbit (16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write, Burst Flash
This product family has been retired and is not recommended for designs. For new and current designs, the S29WS128P and
S29WS256P supersede the S29WS128N and S29WS256N respectively. These are the factory-recommended migration paths.
Please refer to the S29WS-P Family data sheet for specifications and ordering information.
General Description
The Spansion S29WS256/128 are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst mode Flash
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate
data and address pins. These products can operate up to 80 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for
today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
110 nm MirrorBit™ Technology
Hardware (WP#) protection of top and bottom sectors
Dual boot sector configuration (top and bottom)
Offered Packages
Simultaneous Read/Write operation with zero latency
32-word Write Buffer
WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low VCC write inhibit
Sixteen-bank architecture consisting of 16/8 Mwords for WS256N/
128N, respectively
Persistent and Password methods of Advanced Sector Protection
Four 16 Kword sectors at both top and bottom of memory array
254/126 64 Kword sectors (WS256N/128N)
Write operation status bits indicate program and erase operation
completion
Programmable linear (8/16/32) with or without wrap around and
Suspend and Resume commands for Program and Erase
continuous burst read modes
operations
Secured Silicon Sector region consisting of 128 words each for
Unlock Bypass program command to reduce programming time
factory and customer
Synchronous or Asynchronous program operation, independent of
20-year data retention (typical)
burst control register settings
Cycling Endurance: 100,000 cycles per sector (typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4) standard
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Performance Characteristics
Read Access Times
Current Consumption (typical values)
Speed Option (MHz)
Max. Synch. Latency, ns (t
80
80
9
66
80
54
80
Continuous Burst Read @ 80 MHz
Simultaneous Operation (asynchronous)
Program (asynchronous)
38 mA
50 mA
19 mA
19 mA
20 µA
)
IACC
Max. Synch. Burst Access, ns (t
)
11.2
80
13.5
80
BACC
Max. Asynch. Access Time, ns (t
)
80
20
80
13.5
Erase (asynchronous)
ACC
Max. Asynch. Page Access Time, ns (t
)
20
20
Standby Mode (asynchronous)
PACC
Max CE# Access Time, ns (t
Max OE# Access Time, ns (t
)
80
80
CE
)
13.5
13.5
OE
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V ) Per Word
40 µs
9.4 µs
6 µs
CC
Effective Write Buffer Programming (V
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
) Per Word
ACC
150 ms
600 ms
Cypress Semiconductor Corporation
Document Number: 002-01825 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 08, 2016