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S25FL032P0XMFA010 PDF预览

S25FL032P0XMFA010

更新时间: 2024-11-09 20:48:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管内存集成电路
页数 文件大小 规格书
60页 1910K
描述
Flash, 32MX1, PDSO8, SOP-8

S25FL032P0XMFA010 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.32.00.51风险等级:1.68
最大时钟频率 (fCLK):104 MHzJESD-30 代码:S-PDSO-G8
长度:5.28 mm内存密度:33554432 bit
内存集成电路类型:FLASH内存宽度:1
功能数量:1端子数量:8
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32MX1
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:SQUARE封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
编程电压:3 V筛选级别:AEC-Q100
座面最大高度:2.16 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.28 mm
Base Number Matches:1

S25FL032P0XMFA010 数据手册

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S25FL032P  
32-Mbit 3.0 V Flash Memory  
This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede  
S25FL032P. These are the factory-recommended migration paths. Refer to the S25FL-L Family datasheets for specifications and  
ordering information.  
Distinctive Characteristics  
Common Flash Interface (CFI) compliant: allows host system  
Architectural Advantages  
Single power supply operation  
to identify and accommodate multiple flash devices  
Process technology  
– Full voltage range: 2.7 V to 3.6 V read and write operations  
– Manufactured on 0.09 m MirrorBit® process technology  
Package option  
Memory architecture  
– Uniform 64-KB sectors  
– Industry Standard Pinouts  
– 8-pin SO package (208 mils)  
– 16-pin SO package (300 mils)  
Top or bottom parameter block (two 64-KB sectors (top  
or bottom) broken down into 16 4-KB sub-sectors each)  
– 256-byte page size  
– 8-contact USpackage (5 6 mm)  
– 8-contact WSON package (6 8 mm)  
– 24-ball BGA 6 8 mm package, 5 5 pin configuration  
– 24-ball BGA 6 8 mm package, 6 4 pin configuration  
– Backward compatible with the S25FL032A device  
Program  
– Page Program (up to 256 bytes) in 1.5 ms (typical)  
– Program operations are on a page by page basis  
– Accelerated programming mode via 9-V W#/ACC pin  
– Quad Page Programming  
Performance Characteristics  
Speed  
Erase  
– Normal READ (Serial): 40-MHz clock rate  
– FAST_READ (Serial): 104-MHz clock rate (maximum)  
– DUAL I/O FAST_READ: 80-MHz clock rate or  
20 MB/s effective data rate  
– QUAD I/O FAST_READ: 80 MHz clock rate or  
40 MB/s effective data rate  
– Bulk erase function  
– Sector erase (SE) command (D8h) for 64-KB sectors  
– Sub-sector erase (P4E) command (20h) for 4-KB sectors  
– Sub-sector erase (P8E) command (40h) for 8-KB sectors  
Cycling endurance  
– 100,000 cycles per sector typical  
Data retention  
Power saving standby mode  
– Standby Mode 80 A (typical)  
– Deep Power-Down Mode 3 A (typical)  
– 20 years typical  
Device ID  
– JEDEC standard two-byte electronic signature  
– RES command one-byte electroic signature for backward  
compatibility  
Memory Protection Features  
Memory protection  
– W#/ACC pin works in conjunction with Status Register Bits  
to protect specified memory areas  
– Status Register Block Protection bits (BP2, BP1, BP0) in  
status register configure parts of memory as read-only  
One time programmable (OTP) area for permanent, secure  
identification; can be programmed and locked at the factory  
or by the customer  
Cypress Semiconductor Corporation  
Document Number: 002-00650 Rev. *L  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 19, 2017  

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