Datasheet > S2009TB

S2009TB

更新时间： 2024-11-04 20:08:35

品牌	Logo	应用领域
AMCC		以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
42页	1866K
描述
Ethernet Transceiver, CMOS, PBGA208, 23 X 23 MM, COMPACT, TBGA-208

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技术参数
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S2009TB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	23 X 23 MM, COMPACT, TBGA-208
针数：	208	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	8.71
JESD-30 代码：	S-PBGA-B208	长度：	23 mm
功能数量：	1	端子数量：	208
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.65 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	23 mm	Base Number Matches：	1

S2009TB 数据手册

DEVICE

SPECIFICATION

1.6 GBPS QUAD SERIAL BACKPLANE DEVICE

S2009

1.6 GBPS QUAD SERIAL BACKPLANE DEVICE

FEATURES

GENERAL DESCRIPTION

• CMOS Technology

The S2009 facilitates high-speed serial transmission

of data in a variety of applications including Gigabit

Ethernet, serial backplanes, and proprietary point to

point links. The chip provides four separate trans-

ceivers which can be operated individually or locked

together for an aggregate data capacity of >5 Gbps.

• Broad operating rate range (1.3 - 1.6 Gbps)

- 1.6 Gbps

- 1/2 Rate Operation

• Quad Transmitter with Phase-Lock Loop (PLL)

clock synthesis from low speed reference

Each bi-directional channel provides 8B/10B coding/

decoding, parallel-to-serial and serial-to-parallel con-

version, clock generation/recovery, and framing. The

on-chip transmit PLL synthesizes the high-speed

clock from a low-speed reference. The on-chip quad

receive PLL is used for clock recovery and data re-

timing on the four independent data inputs. The

transmitter and receiver each support differential

PECL-compatible I/O for copper or fiber optic com-

ponent interfaces with excellent signal integrity. Lo-

cal loopback mode allows for system diagnostics.

The chip requires a +3.3 V power supply and dissi-

pates 2.65 watts.

• Quad Receiver PLL provides clock and data

recovery

• Internally series terminated TTL outputs

• On-chip 8B/10B line encoding and decoding for

four separate parallel 8-bit channels

• 32-bit parallel TTL interface with internal series

terminated outputs

• Low-jitter serial PECL interface

• Individual local loopback control

• JTAG 1149.1 Boundary scan on low speed I/O

signals

• Interfaces with coax, twinax, or fiber optics

Figure 1 shows the S2009 and S2204 in a Gigabit

Ethernet application. Figure 2 combines the S2009

with a crosspoint switch to demonstrate a serial

backplane application. Figure 3 is the input/output

diagram. Figures 4 and 5 show the transmit and

receive block diagrams, respectively.

• Single +3.3 V supply, 2.65 W power dissipation

• Compact 23 mm x 23 mm 208 pin

TBGA package

APPLICATIONS

• Ethernet Backbones

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

Figure 1. Typical Quad Gigabit Ethernet Application

GE INTERFACE

SERIAL BP DRIVER

MAC

(ASIC)

MAC

(ASIC)

TO SERIAL BACKPLANE

QUAD

GIGABIT

ETHERNET

S2204

S2009

MAC

(ASIC)

INTERFACE

MAC

(ASIC)

February 9, 2001 / Revision C

12 3 4 5 6 7...42

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