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S1C33401

更新时间: 2024-10-02 12:33:31
品牌 Logo 应用领域
爱普生 - EPSON /
页数 文件大小 规格书
12页 219K
描述
CMOS 32-bit Single Chip Microcomputer

S1C33401 数据手册

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S1C33401  
CMOS 32-bit Single Chip Microcomputer  
32-bit C33 ADV RISC Core with 8K-byte Cache  
Low Power Consumption  
Multiply Accumulation  
Built-in 32K-byte + 1K-byte RAM  
10-bit ADC  
4-ch. SIO  
10-ch. PWM Timer with DA16 Mode  
Card Interfaces  
High-speed DMA, Intelligent DMA  
DESCRIPTIONS  
The S1C33401 is a 32-bit RISC-type microcomputer originally developed for embedded applications by Seiko Epson.  
The S1C33401 is built around the C33 ADV core block that includes the CPU, MMU, cache, and modules that allow  
various external memory and I/O devices to be connected directly, and incorporates a bus block that includes the DMA  
controller and other control units. In addition to these primary units, the S1C33401 incorporates a basic peripheral circuit  
block that includes an interrupt controller, timers, serial interfaces, card interfaces, input/output ports, and A/D  
converter, and an extended peripheral circuit block that includes a chip ID register, RTC, and other components.  
The S1C33401 is manufactured by a 0.18 μm fine-pattern CMOS process, backed by sophisticated clock control  
functions, and can operate at higher speed with less power than ever before. In addition to its use as an embedded-type  
processor in various portable systems, the S1C33401 features a built-in C33 ADV CPU to provide enhanced functionality  
for multimedia support while retaining upward compatibility with the conventional C33 STD CPU, making it an ideal  
solution to the requirements of mobile multimedia applications.  
Product Lineup  
Model No.  
Package  
S1C33401F00A∗∗∗  
S1C33401B00A∗∗∗  
QFP20-184pin  
PFBGA-160pin  
FEATURES  
CORE  
CPU  
• Original Seiko Epson 32-bit RISC-type CPU – C33 ADV  
• Internal 32-bit data processing  
• 4GB address space  
• Powerful instruction set  
- Code length:  
16 bits per instruction  
- Number of instructions: 164  
- Main instructions executable in 1 cycle (including immediate-extended instructions, each consisting of two to three  
instructions)  
- 15.15 ns per instruction (when operating at 66 MHz, max.)  
• Multimedia support functions  
- Built-in 32-bit × 16-bit multiplier  
- 16 × 16, 32 × 16 and 32 × 32-bit multiplication  
- 16 × 16, 32 × 16 and 32 × 32-bit multiply-accumulate operations  
- Repeated execution by loop and repeat instructions  
- Rounding to minimum/maximum values by saturation instruction  
- ALU instruction execution with post-shift  
High-speed Bus Control Unit (HBCU)  
• Controls memory access by the CPU by dividing 4GB logical space into eight 512MB blocks.  
• Manages MMU, CCU, and ASID processing in each block.  
• Capable of multiplexing logical space using ASID and mirroring physical space.  
• Can simultaneously process A0RAM data read/write operations and instruction fetching from cache.  
SEIKO EPSON CORPORATION  

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