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S1C33E07 PDF预览

S1C33E07

更新时间: 2024-10-02 12:04:51
品牌 Logo 应用领域
爱普生 - EPSON 控制器
页数 文件大小 规格书
6页 344K
描述
CMOS 32-bit Application Specific Controller

S1C33E07 数据手册

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S1C33E07  
CMOS 32-bit Application Specific Controller  
32-bit RISC CPU-Core Optimized for SoC (EPSON S1C33 PE)  
Built-in 8KB RAM  
SDRAM Controller with Burst Control  
Generic DMA Controller (HSDMA/IDMA)  
6-ch. PWM Control Timer/Counter  
Supports Several Interfaces  
SIO with FIFO (IrDA1.0), SPI, I2S and DCSIO  
5-ch. ADC for Analog Input  
Built-in LCD Controller with 12KB IVRAM  
„ DESCRIPTIONS  
The S1C33E07 is a high cost performance 32-bit RISC controller for specific applications that require a lot of  
general-purpose I/O, a powerful PWM Timer/Counter function, several serial interfaces including USB-FS device  
controller, an ADC and a LCD display system, such as middle-low range electronic dictionaries and label writers/printers.  
The S1C33E07 consists of a 32-bit RISC CPU-Core, generic DMA controller, USB-FS device controller, PWM control  
Timer/Counter, several interfaces (SIO including IrDA1.0, SPI, I2S and DCSIO), ADC, RAM/Shared IVRAM and RTC  
implemented by EPSON SoC design technology using 0.18 μm Mixed Analog Low CMOS Process.  
„ FEATURES  
Technology  
0.18 μm AL-4-Layers mixed analog low power CMOS process technology  
CPU  
EPSON original C33 PE 32-bit RISC CPU-Core with AMBA bus optimized for SoC  
Max. 60 MHz operation  
Internal 2-stage pipeline and 4 instruction queues  
Instruction set: 128 instructions (16-bit fixed length)  
Basic instructions are compatible with the S1C33 32-bit RISC Cores.  
Dual AMBA bus system for CPU and LCDC  
Internal Memories  
8KB RAM  
12KB IVRAM (used as general-purpose RAM or VRAM)  
2KB DST RAM (used as general-purpose RAM or IDMA descriptor table RAM)  
Oscillator Circuit / PLL  
OSC3 Oscillator Circuit  
Crystal oscillation: 5 MHz min. to 48 MHz max.  
Ceramic oscillation: 5 MHz min. to 48 MHz max.  
External clock input: 5 MHz min. to 48 MHz max.  
PLL  
PLL input frequency: 5 MHz min. to 50 MHz max.  
PLL output frequency: 25 MHz min. to 90 MHz max.  
Multiplication rate: 1 ~ 15.  
OSC1 Oscillator Circuit  
Crystal oscillation/External clock input: 32.768 kHz typ.  
High Speed Bus (HB) Modules  
SRAMC (SRAM Controller)  
25-bit address lines and 8/16-bit selectable data bus  
UP to a 512M-byte (A[24:0]) address space is provided for each chip enable signal.  
Max. 8 chip enable signals are available to connect external devices.  
Programmable bus wait cycle (0 to 7 cycles)  
Supports external wait signals.  

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