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S1C37109W PDF预览

S1C37109W

更新时间: 2024-11-21 21:10:15
品牌 Logo 应用领域
精工 - SEIKO 外围集成电路
页数 文件大小 规格书
12页 95K
描述
32-BIT, 90MHz, RISC MICROCONTROLLER, PLGA424, 17 X 17 MM, 1 MM HEIGHT, 0.80 MM PITCH, CFLGA-424

S1C37109W 数据手册

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PF1041-04  
S1C37109/S1C37109W  
32-bit Single Chip RISC Microcomputer  
DESCRIPTION  
The S1C37109 and S1C37109W are single-chip RISC microcomputers that contain Hitachi 32-bit RISC proces-  
sor SH7709-compatible chip as the CPU. In addition to the existing peripheral functions of the SH7709, they  
have a built-in LCD controller compatible with SEIKO EPSON S1D13504 and incorporate various interface  
functions as companion functions such as PCMCIA, compact flash, keyboard and mouse, and ISA bus subset.  
These peripheral functions make it possible to configure an application system for portable information equip-  
ment using LCD or POS and other terminal equipment by adding only a few external circuits (e.g., memory and  
buffer). Furthermore, the low-power design of these devices helps to maximize the battery life of portable and  
mobile equipment.  
The S1C37109 and S1C37109W realizes an excellent cost-performance ratio with all the functions necessary  
for embedded systems in portable information equipment, multi-media equipment, etc. integrated on a single  
chip.  
The S1C37109W is a version that supports Windows CE.  
FEATURES  
[CPU functions]  
• Dividable cache (4K-byte/2-way cache memory + 4K-  
byte memory)  
CPU  
• 32-bit RISC processor compatible with SH7709  
• 32-bit internal data bus  
• 32-bit general-purpose register × 16  
• RISC instruction set  
• Instruction execution rate: One instruction per cycle  
(for basic instructions)  
• 4G-byte logical address space  
• 372M-byte physical memory space  
• Space identification ASID  
• Built-in multiplier  
Interrupt controller  
• Six external interrupt pins (NMI, IRQ5–IRQ1)  
• Internal interrupts: Interrupt priorities set for each  
module  
User break control  
• Break channel × 2  
• Allows address, data value, access type, and data  
size to be set as break conditions  
• Supports successive break  
• Five-stage pipelining  
Bus state controller  
Memory management unit (MMU)  
• 4G-byte address space,  
• Physical address space divided into six areas of up to  
64M bytes, with the following functions selectable for  
each  
256 address space (ASID 8 bits)  
• Paging method  
– Bus size (8, 16, or 32 bits)  
– Number of wait cycles  
• Supports multiple page sizes: 1K or 4K bytes  
• 128-entry, 4-way set associative TLB  
• Supports specification of replacement ways by soft-  
ware and random replacement algorithm  
• Can directly access TLB contents by address map-  
ping  
– SRAM, DRAM, synchronous DRAM, and burst  
ROM mapping into directly accessible area  
– Supports PCMCIA interface  
– Chip-select signal output for each area  
• DRAM and synchronous DRAM refresh function  
– Programmable refresh intervals  
– Supports CAS-before-RAS refresh and self-refresh  
– Supports power-down DRAM  
Cache memory  
• 8K-byte unified cache  
• 128-entry, 4-way set-associative (8K-byte cache),  
16 bytes/line  
• Write-back/write-through selectable LRU replace-  
ment algorithm  
• One-stage write-back buffer  
• DRAM and synchronous DRAM burst-access func-  
tion  
• Little endian  

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