RTL8306SD/RTL8306SDM
Datasheet
7.3.9. Reg.0.14 PHY Digital Loopback Return to Internal.............................................................................................50
7.3.10.
7.3.11.
1.8V Power Generation ...................................................................................................................................51
Crystal/Oscillator ............................................................................................................................................51
8.
ADVANCED FUNCTION DESCRIPTION...................................................................................................................52
8.1.
8.2.
ACL FUNCTION .........................................................................................................................................................52
VLAN FUNCTION ......................................................................................................................................................53
8.2.1. Description...........................................................................................................................................................53
8.2.2. Port-Based VLAN.................................................................................................................................................55
8.2.3. IEEE 802.1Q Tagged-VID Based VLAN ..............................................................................................................56
8.2.4. VLAN Packet Trap to CPU Port...........................................................................................................................58
8.2.5. PVID.....................................................................................................................................................................58
8.3.
QOS FUNCTION..........................................................................................................................................................59
8.3.1. Bandwidth Control ...............................................................................................................................................59
8.3.2. Priority Assignment..............................................................................................................................................61
8.4.
LOOKUP TABLE FUNCTION ........................................................................................................................................65
8.4.1. Function Description............................................................................................................................................65
8.4.2. 4-Way Direct Mapping Algorithm........................................................................................................................65
8.4.3. Lookup and CAM Table Definition ......................................................................................................................65
8.5.
8.6.
IEEE 802.1P REMARKING FUNCTION.........................................................................................................................66
MIBS FUNCTION........................................................................................................................................................67
8.6.1. MIB Counter Description.....................................................................................................................................67
8.6.2. MIB Counter Enable/Clear ..................................................................................................................................68
8.6.3. MIB Counter Timeout...........................................................................................................................................68
8.7.
8.8.
8.9.
8.10.
8.11.
STORM FILTER FUNCTION..........................................................................................................................................68
CPU INTERRUPT FUNCTION .......................................................................................................................................70
IGMP & MLD SNOOPING FUNCTION.........................................................................................................................71
CPU TAG FUNCTION..................................................................................................................................................73
IEEE 802.1X FUNCTION.............................................................................................................................................75
8.11.1.
8.11.2.
8.12.
8.13.
8.14.
8.15.
Port-Based Access Control..............................................................................................................................75
MAC-Based Access Control.............................................................................................................................76
IEEE 802.1D FUNCTION ............................................................................................................................................77
INPUT & OUTPUT DROP FUNCTION ............................................................................................................................78
PORT MIRRORING ......................................................................................................................................................80
LED FUNCTION..........................................................................................................................................................81
8.15.1.
8.15.2.
RTL8306SD/RTL8306SDM Controlling LED .................................................................................................83
CPU Controlling LED .....................................................................................................................................84
9.
REGISTER DESCRIPTIONS.........................................................................................................................................85
9.1.
9.2.
REGISTER LIST...........................................................................................................................................................85
PHY 0 REGISTERS......................................................................................................................................................87
9.2.1. PHY 0 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................87
9.2.2. PHY 0 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................88
9.2.3. PHY 0 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1...........................................................................................88
9.2.4. PHY 0 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2...........................................................................................89
9.2.5. PHY 0 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................89
9.2.6. PHY 0 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................90
9.2.7. PHY 0 Register 16 (Page 0, 1, 2, 3): Global Control 0........................................................................................91
9.2.8. PHY 0 Register 18 (Page 0, 1): Global Control 2................................................................................................92
9.2.9. PHY 0 Register 19 (Page 0, 1): Global Control 3................................................................................................92
9.2.10.
9.2.11.
PHY 0 Register 22 (Page 0, 1): Port 0 Control Register 0..............................................................................93
PHY 0 Register 24 (Page 0, 1): Port 0 Control Register 1..............................................................................94
9.3.
PHY 1 REGISTERS......................................................................................................................................................94
9.3.1. PHY 1 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................94
9.3.2. PHY 1 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................94
6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
iv
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