RFM95/96/97/98(W)
Section
Page
Figure 1. Block Diagram ...............................................................................................................................................9
Figure 2. Pin Diagrams ...............................................................................................................................................10
Figure 3. RFM95/96/97/98(W) Block Schematic Diagram ..........................................................................................20
Figure 4. LoRaTM Modem Connectivity ......................................................................................................................23
Figure 5. Interrupts generated in the case of successful frequency hopping communication. .....................................28
Figure 6. Channel activity detection (CAD) time as a function of spreading factor ......................................................39
Figure 7. Consumption Profile of the LoRa CAD Process ............................................................................................40
Figure 8. OOK Peak Demodulator Description .............................................................................................................44
Figure 9. Floor Threshold Optimization ........................................................................................................................45
Figure 10. Bit Synchronizer Description .......................................................................................................................46
Figure 11. FEI Process .................................................................................................................................................47
Figure 12. Startup Process ...........................................................................................................................................50
Figure 13. Time to Rssi Sample ...................................................................................................................................52
Figure 14. Tx to Rx Turnaround ...................................................................................................................................52
Figure 15. Rx to Tx Turnaround ...................................................................................................................................52
Figure 16. Receiver Hopping ........................................................................................................................................53
Figure 17. Transmitter Hopping ....................................................................................................................................53
Figure 18. Timer1 and Timer2 Mechanism ...................................................................................................................57
Figure 19. Sequencer State Machine ...........................................................................................................................59
Figure 20. RFM95/96/97/98(W) Data Processing Conceptual View .............................................................................60
Figure 21. FIFO and Shift Register (SR) ......................................................................................................................61
Figure 22. FifoLevel IRQ Source Behavior ...................................................................................................................62
Figure 23. Sync Word Recognition ...............................................................................................................................63
Figure 24. Continuous Mode Conceptual View ............................................................................................................65
Figure 25. Tx Processing in Continuous Mode .............................................................................................................65
Figure 26. Rx Processing in Continuous Mode ............................................................................................................66
Figure 27. Packet Mode Conceptual View ...................................................................................................................67
Figure 28. Fixed Length Packet Format .......................................................................................................................68
Figure 29. Variable Length Packet Format ...................................................................................................................69
Figure 30. Unlimited Length Packet Format .................................................................................................................69
Figure 31. Manchester Encoding/Decoding .................................................................................................................73
Figure 32. Data Whitening Polynomial .........................................................................................................................74
Figure 33. SPI Timing Diagram (single access) ...........................................................................................................75
Figure 34. TCXO Connection .......................................................................................................................................76
Figure 35. RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................78
Figure 36. Temperature Sensor Response ..................................................................................................................83
Figure 37. POR Timing Diagram ................................................................................................................................108
Figure 38. Manual Reset Timing Diagram ..................................................................................................................109
Figure 39. Listen Mode: Principle ...............................................................................................................................109
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