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R5107G291A-TR-F

更新时间： 2024-11-06 15:49:07
品牌 Logo 应用领域
理光 - RICOH 光电二极管
页数 文件大小 规格书
2页 322K
描述
Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO8, ROHS COMPLIANT, SSOP-8

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R5107G291A-TR-F 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：LSSOP,针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N其他特性：DETECTOR THRESHOLD VOLTAGE IS 2.9V
可调阈值：NO模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e6
长度：2.9 mm信道数量：1
功能数量：1端子数量：8
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.3 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：0.9 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Bismuth (Sn/Bi)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：2.8 mm
Base Number Matches：1

R5107G291A-TR-F 数据手册

 浏览型号R5107G291A-TR-F的Datasheet PDF文件第2页 
R5107G Series  
Watchdog Timer Equipped with Manual Reset with VD  
The R5107G Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single chip.  
R5107G monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset signal when a  
malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted with an external capacitor  
with a high degree of accuracy. The R5107G is equipped with the function that inhibits clock monitoring of the WDT (INH) and manual reset  
(MR) that also stops the VD.  
FEATURES  
• Supply Current (ISS) ························Typ. 11μA (VDD=-VDET+0.5V,  
Clock pulse input)  
• Operating Voltage Range (VDD) ······0.9V to 6.0V  
(VD Section)  
• Output Delay Time (tPLH)·················Typ. 370ms (CD=0.1μF)  
<
• Output Delay Time Accuracy··········± 16% (-40°C Topt 105°C)  
=
=
(WDT Section)  
• Watchdog Timeout Period(tWD)·······Typ. 310ms (CTW=0.1μF)  
•
•
•
Detector Threshold Range (-VDET  
Detector Threshold Accuracy ··········± 1%  
Temp. coeff. of Detector Threshold ···Typ. ± 100ppm/°C  
)
···1.5V to 5.5V (internally fixed)  
• Reset Hold Time of WDT(tWR)·········Typ. 34ms (CTW=0.1μF)  
<
•
Watchdog Timeout Period Accuracy ····± 33% (-40°C Topt 105°C)  
• Package··········································SSOP-8G  
=
=
°
°
°
(The above shows specification at Topt=25 C. Design assurance value at -40 C  
Topt  
105 C is also available. For details, please refer to the datasheet.)  
=
=
BLOCK DIAGRAMS  
TYPICAL APPLICATION  
R5107Gxx1A  
R5107Gxx1C  
(Nch. open drain output)  
(CMOS output)  
Power Supply  
Microprocessor  
VDD  
MR  
MR  
R
V
DD  
VDD  
8
6
2
3
RESETB  
R5107Gxx1A  
1
5
VDD  
INH  
MR  
CD  
RESET  
I/O  
C
D
CD  
Series  
SCK  
Vref2  
Vref1  
Vref2  
Vref1  
GND  
SCK  
GND  
SCK  
CTW  
CTW  
SW SW  
CTW  
7
GND  
4
WATCHDOG  
TIMER  
CLOCK  
DETECTOR  
WATCHDOG  
TIMER  
CLOCK  
DETECTOR  
CTW  
CD  
RESETB  
INH  
INH  
RESETB  
SELECTION GUIDE  
.
xx.  
:
Specify the detector threshold within the range 1.5V  
in 0.1V steps.  
(.  
15  
.
) to 5.5V (  
.
55  
.
)
Package  
Quantity per Reel  
Part No.  
SSOP-8G  
3,000 pcs  
R5107G  
.
xx.  
1.  
∗-TR-F  
.
: Select the output type from (  
.
A
.
) Nch. open drain or (  
.
C
.
) CMOS.  
.
∗
PACKAGE (Top View)  
TIMING CHART  
SSOP-8G  
+VDET  
DD  
V
8
7 6 5  
-VDET  
V
INH  
1
2
3
4
V
MR  
t
PHL  
t
PHL  
t
PLH  
tPLH  
1
2
RESETB Output pin for Reset "L" signal  
MR  
Manual reset pin  
+VTCD  
-VTCD  
VCD  
Ext. Cap. pin for setting output  
delay time of VD  
3
CD  
tWD  
tWDI  
tWD  
Vref2H  
4
5
6
GND  
SCK  
INH  
Ground pin  
Watchdog timer clock input pin  
Inhibit pin  
VCTW  
Vref2L  
tWR  
tWR  
Ext. Cap. pin for setting reset and  
watchdog timeout period of WDT  
Power supply pin  
VSCK  
7
8
CTW  
VDD  
tMR  
t
PLH  
VRESETB  
APPLICATION  
∗tPHL : Output delay time  
∗tWDI : tWD/10 (SCK pulses input during this period are ignored.)  
• Monitoring of the power system of devices equipped with microprocessors  
No.EK-170-091101  
CMOS Microprocessor Supervisory  
12

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