Datasheet > QL30250PB256I

QL30250PB256I

更新时间： 2024-11-06 06:06:15

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其他 - ETC		栅
页数	文件大小	规格书
17页	532K
描述
25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

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QL30250PB256I 数据手册

QL3025 pASIC 3 FPGA Data Sheet

25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance

and High Density

• • • • • •

Four Low-Skew Distributed

Networks

Device Highlights

• Two array clock/control networks available

to the logic cell flip-flop clock, set and reset

inputs — each driven by an input-only pin

High Performance & High Density

• 25,000 Usable PLD Gates with 204 I/Os

• 300 MHz 16-bit Counters,

• Two global clock/control networks available

to the logic cell; F1, clock set, reset inputs

and the input, I/O register clock, reset, and

enable inputs as well as the output enable

control — each driven by an input-only or

I/O pin, or any logic cell output or I/O cell

feedback

400 MHz Datapaths

• 0.35 µm four-layer metal non-volatile

CMOS process for smallest die sizes

Easy to Use / Fast Development

Cycles

• 100% routable with 100% utilization and

High Performance

complete pin-out stability

• Input + logic cell + output total delays

• Variable-grain logic cells provide high

under 6 ns

performance and 100% utilization

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V buses

for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O Cells with individually controlled

Registered Input Path and Output Enables

Total of 204 I/O Pins

• 196 bidirectional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• Four High Drive input-only pins

• Four High Drive input-only/distributed

network pins

Figure 1: 672 pASIC 3 Logic Cells

•

www.quicklogic.com

12 3 4 5 6 7...17

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