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PT7V4050TACFB44.736/24.704

更新时间： 2024-11-07 13:25:27
品牌 Logo 应用领域
美台 - DIODES /
页数 文件大小 规格书
7页 127K
描述
PLL/Frequency Synthesis Circuit,

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PT7V4050TACFB44.736/24.704 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：compliant风险等级：5.67
Is Samacsys：NBase Number Matches：1

PT7V4050TACFB44.736/24.704 数据手册

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Data Sheet  
PT7V4050  
PLL with quartz stabilized VCXO  
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||  
Features  
Description  
•
•
•
•
•
•
•
•
PLL with quartz stabilized VCXO  
The device is composed of a phase-lock loop with an  
integrated VCXO for use in clock recovery, data re-  
timing, frequency translation and clock smoothing  
applications in telecom and datacom systems.  
Loss of signals alarm  
Return to nominal clock upon LOS  
Input data rates from 8 kb/s to 65 Mb/s  
Tri-state output  
Crystal Frequencies Supported: 12.000~50.000 MHz.  
User defined PLL loop response  
NRZ data compatible  
Single +5.0V power supply  
Block Diagram  
RCLK  
CLKIN  
DATAIN  
Phase Detector &  
Loss Of Signal  
Circuit  
RDATA  
LOS  
HIZ  
PHO  
CLK1  
VC  
LOSIN  
VCXO  
Divider  
CLK2  
OPN  
OPP  
Op  
Amp  
OPOUT  
Ordering Information  
Frequencies using at CLK1 (MHz)  
PT7V4050  
T
B
C
G
A
49.408 / 12.352  
CLK2 Frequency  
12.000  
12.288  
16.384  
18.936  
24.576  
30.720  
38.880  
47.457  
12.624  
16.777  
20.000  
24.704  
32.000  
40.000  
49.152  
19.440  
13.00  
16.896  
20.480  
25.000  
32.768  
41.2416  
49.408  
35.328  
16.000  
17.920  
22.1184  
27.000  
33.330  
41.943  
50.000  
40.960  
16.128  
18.432  
22.579  
28.000  
34.368  
44.736  
DeviceType  
CLK1 Frequency  
16-pinclock recoverymodule  
A: 5.0V supply voltage  
B: 3.3V supply voltage  
PackageLeads  
T: Thru-Hole  
G: Surface Mount  
C: 20ppm  
±
F: 32ppm  
±
CLK2 Divider  
±
G: 50ppm  
H:  
A: Divide by 2 E: Divide by 32  
B: Divide by 4 F: Divide by 64  
C: Divide by 8 G: Divide by 128  
D: Divide by 16 H: Divide by 256  
K: Disable  
±
100ppm  
Temperature Range  
Note: CLK1 up to 40.960MHz for both 5V and  
°
°
C
C: 0 C to 70  
o
o
3.3V for temperature -40 Cto 85 C; CLK1 up to  
°
°
C
T: -40 C to 85  
o
o
50MHz for both 5V and 3.3V for temperature 0 C to 70 C.  
PT0125(02/06)  
Ver:2  
1
1234567

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