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PT5061B PDF预览

PT5061B

更新时间: 2024-11-10 23:29:35
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描述
Analog IC

PT5061B 数据手册

 浏览型号PT5061B的Datasheet PDF文件第2页浏览型号PT5061B的Datasheet PDF文件第3页浏览型号PT5061B的Datasheet PDF文件第4页 
PT5060 Series  
9-W +5V-Input Dual-Output  
Integrated Switching Regulator  
SLTS027B  
(Revised 12/19/2001)  
Features  
Single Device:  
Description  
+ꢀV Input  
The PTꢀ060 series of dual-output  
Integrated Switching Regulators (ISRs)  
provide a complimentary ±±1V or ±±ꢀV  
from a single +ꢀV input. Applications  
include systems that require power for  
analog interface circuitry, such as D/A  
and A/D converters, and Op Amps. The  
output voltage can be adjusted with an  
external resistor. These ISRs are made  
available in a ±1-pin single in-line pin  
(SIP) package. Note that these modules  
are are not short-circuit protected.  
Complimentary Dual Output:  
±±1V, ±±ꢀV  
Wide Input Voltage Range  
8ꢀ% Efficiency  
Adjustable Output Voltage  
Laser-trimmed  
Pin-Out Information  
Ordering Information  
PT 5061¨ = ±±1 Volts  
PT 5062¨ = ±±ꢀ Volts  
Pin Function  
±
Vo1  
GND  
Vin  
Standard Application  
1
PT Series Suffix  
(PT1234x)  
Vo adj  
3
4
Vin  
Case/Pin  
O rder  
Package  
11  
Configuration  
Suffix  
Code *  
1
–Vo2  
+Vo1  
Vin  
Vin  
3,4,5  
PT5060  
Vertical  
Horizontal  
SMD  
Vertical, Side Tabs  
Horizontal, Side Tabs  
SMD, Side Tabs  
N
A
C
R
G
B
(ECD)  
(ECA)  
(ECC)  
(ECE)  
(ECG)  
(ECK)  
8,9,10  
6GND  
7
GND  
2,6,7  
+
8
+Vo±  
C1  
100µF  
9
+Vo±  
COM  
COM  
±0  
±±  
±1  
+Vo±  
Vo Adj  
* Previously known as package style 300.  
Do Not Connect  
C± = Required ±00µF electrolytic  
(Reference the applicable package code drawing  
for the dimensions and PC board layout)  
Specifications (Unless otherwise stated, Ta =1ꢀ°C, Vin =+ꢀV, Io =Iomax, C± =±00µF)  
PT5060 SERIES  
Characteristics  
Symbol  
Conditions  
Min  
Typ  
Max  
Units  
Output Current  
Io  
Over Vin range  
Vo± = +±1V  
Vo1 = –±1V  
0.0ꢀ  
0.0ꢀ  
0.ꢀ0  
0.1ꢀ  
A
(±)  
(±)  
Vo± = +±ꢀV  
Vo1 = –±ꢀV  
0.0ꢀ  
0.0ꢀ  
0.40  
0.10  
A
(1)  
(3)  
Current Limit  
Inrush Current  
Ilim  
±ꢀ0  
%Iomax  
Iir  
ttr  
On start up  
ꢀ.ꢀ  
1
A
mSec  
Input Voltage Range  
Vin  
Over Io range  
4.7ꢀ  
+Vo –±  
V
Output Voltage Tolerance  
Vo  
Over Vin and Io ranges  
+Vo±  
–Vo1  
±±.ꢀ  
±ꢀ  
±3.0  
±±0  
%Vo  
Ta= 0°C to SOA limit (3)  
Line Regulation  
Load Regulation  
Vo Ripple (pk-pk)  
Regline  
Regload  
Vn  
Over Vin range  
±0.ꢀ  
±0.ꢀ  
±±.0  
±±.0  
%Vo  
%Vo  
0.± Io Iomax  
10MHz bandwidth  
+Vo±  
–Vo1  
±±.ꢀ  
±1  
±3  
±3  
%Vo  
Transient Response  
ttr  
1ꢀ% load change  
±00  
3
µSec  
%Vo  
Vos  
Vo over/undershoot  
Efficiency  
η
Io=0.1A each output  
Over Vin and Io ranges  
0
8ꢀ  
6ꢀ0  
%
Switching Frequency  
Operating Temperature Range  
Storage Temperature  
Mechanical Shock  
ƒs  
kHz  
°C  
°C  
Ta  
Ts  
+8ꢀ (4)  
+±1ꢀ  
–40  
Per Mil-STD-883D, Method 1001.3,  
± msec, Half Sine, mounted to a fixture  
ꢀ00  
G’s  
Mechanical Vibration  
Per Mil-STD-883D, Method 1007.1  
10-1000 Hz, Soldered in a PC board  
±ꢀ  
G’s  
Weight  
6.ꢀ  
grams  
Notes: (1)Do not operate thes negative output rail of these ISRs below the minimum load.  
(2)ISRs based on  
a boost topology are not short-circuit protected.  
(3)The inrush current stated is above the normal input current for the associated output load.  
(4)See Safe Operating Area curves or consult the factory for the appropr.iate derating  
For technical support and more information, see inside back cover or visit www.ti.com  

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