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PSD853F2V-12MT PDF预览

PSD853F2V-12MT

更新时间: 2024-11-07 10:02:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 并行IO端口微控制器和处理器外围集成电路
页数 文件大小 规格书
110页 1732K
描述
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PSD853F2V-12MT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, QFP-52
针数:52Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
最长访问时间:1.2e-7 nsJESD-30 代码:S-PQFP-G52
JESD-609代码:e4长度:10 mm
I/O 线路数量:27端口数量:4
端子数量:52最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP52,.52SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedROM大小(位):1048576 Bits
座面最大高度:2.35 mm最大待机电流:0.0001 A
子类别:Other Microprocessor ICs最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
紫外线可擦:N宽度:10 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PSD853F2V-12MT 数据手册

 浏览型号PSD853F2V-12MT的Datasheet PDF文件第2页浏览型号PSD853F2V-12MT的Datasheet PDF文件第3页浏览型号PSD853F2V-12MT的Datasheet PDF文件第4页浏览型号PSD853F2V-12MT的Datasheet PDF文件第5页浏览型号PSD853F2V-12MT的Datasheet PDF文件第6页浏览型号PSD853F2V-12MT的Datasheet PDF文件第7页 
PSD813F2, PSD833F2  
PSD834F2, PSD853F2, PSD854F2  
Flash In-System Programmable (ISP)  
Peripherals for 8-bit MCUs, 5V  
PRELIMINARY DATA  
FEATURES SUMMARY  
FLASH IN-SYSTEM PROGRAMMABLE (ISP)  
Figure 1. Packages  
PERIPHERAL FOR 8-BIT MCUS  
DUAL BANK FLASH MEMORIES  
UP TO 2 Mbit OF PRIMARY FLASH  
MEMORY (8 Uniform Sectors, 32K x8)  
UP TO 256 Kbit SECONDARY FLASH  
MEMORY (4 Uniform Sectors)  
Concurrent operation: READ from one  
memory while erasing and writing the  
other  
PQFP52 (M)  
UP TO 256 Kbit BATTERY-BACKED SRAM  
27 RECONFIGURABLE I/O PORTS  
ENHANCED JTAG SERIAL PORT  
PLD WITH MACROCELLS  
Over 3000 Gates of PLD: CPLD and  
DPLD  
CPLD with 16 Output Macrocells (OMCs)  
and 24 Input Macrocells (IMCs)  
DPLD - user defined internal chip select  
decoding  
PLCC52 (J)  
27 INDIVIDUALLY CONFIGURABLE I/O  
PORT PINS  
The can be used for the following functions:  
MCU I/Os  
PLD I/Os  
Latched MCU address output  
Special function I/Os.  
16 of the I/O ports may be configured as  
open-drain outputs.  
TQFP64 (U)  
IN-SYSTEM PROGRAMMING (ISP) WITH  
JTAG  
Built-in JTAG compliant serial port allows  
full-chip In-System Programmability  
Efficient manufacturing allow easy  
product testing and programming  
HIGH ENDURANCE:  
100,000 Erase/WRITE Cycles of Flash  
Memory  
Use low cost FlashLINK cable with PC  
PAGE REGISTER  
1,000 Erase/WRITE Cycles of PLD  
15 Year Data Retention  
Internal page register that can be used to  
expand the microcontroller address space  
by a factor of 256  
5V±10% SINGLE SUPPLY VOLTAGE  
STANDBY CURRENT AS LOW AS 50µA  
PROGRAMMABLE POWER MANAGEMENT  
June 2004  
1/110  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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