Introduction
1.3
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
SRAM
48 KB
Code Flash Data Flash
512 KB 64 KB
JTAG
JTAG port
Instructions
Nexus port
SRAM
Flash
controller
e200z0h
Nexus 2+
(Master)
Nexus
controller
Data
NMI
(Slave)
(Master)
SIUL
Voltage
regulator
(Slave)
Interrupt requests
from peripheral
blocks
(Slave)
NMI
MPU
registers
INTC
Clocks
CMU
FMPLL
RTC
MC_RGM MC_CGM MC_ME MC_PCU
SSCM
STM
PIT
BAM
SWT
ECSM
Peripheral bridge
SIUL
36 Ch.
ADC
2 x
eMIOS
4 x
LINFlex
3 x
DSPI
6 x
FlexCAN
2
CTU
I C
Reset control
Interrupt
request
External
interrupt
request
IMUX
WKPU
GPIO and
pad control
Interrupt
request with
wakeup
. . .
. . .
. . .
. . .
. . .
I/O
functionality
Legend:
ADC
BAM
Analog-to-Digital Converter
Boot Assist Module
MC_ME
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
Mode Entry Module
FlexCAN Controller Area Network
CMU
CTU
DSPI
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
MPU
Nexus
NMI
Memory Protection Unit
Nexus Development Interface (NDI) Level
Non-Maskable Interrupt
eMIOS
FMPLL
I C
IMUX
INTC
JTAG
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
PIT
RTC
SIUL
SRAM
SSCM
STM
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
2
JTAG controller
LINFlex
ECSM
Serial Communication Interface (LIN support)
Error Correction Status Module
SWT
WKPU
Software Watchdog Timer
Wakeup Unit
MC_CGM Clock Generation Module
Figure 1. Block diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 14
NXP Semiconductors
5