RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
CONTENTS
1
2
3
4
5
6
7
8
9
FEATURES ....................................................................................................................... 1
APPLICATIONS ................................................................................................................ 3
REFERENCES.................................................................................................................. 4
APPLICATION EXAMPLES .............................................................................................. 5
BLOCK DIAGRAM ............................................................................................................ 6
DESCRIPTION.................................................................................................................. 7
PIN DIAGRAM................................................................................................................... 9
PIN DESCRIPTION..........................................................................................................11
FUNCTIONAL DESCRIPTION........................................................................................ 33
9.1
9.2
HIGH-LEVEL DATA LINK CONTROL PROTOCOL ........................................... 33
RECEIVE CHANNEL ASSIGNER...................................................................... 34
9.2.1
9.2.2
9.2.3
9.2.4
LINE INTERFACE............................................................................. 34
PRIORITY ENCODER...................................................................... 34
CHANNEL ASSIGNER ..................................................................... 35
LOOPBACK CONTROLLER ............................................................ 35
9.3
9.4
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ........................ 35
9.3.1
9.3.2
HDLC PROCESSOR........................................................................ 36
PARTIAL PACKET BUFFER PROCESSOR..................................... 36
RECEIVE DMA CONTROLLER......................................................................... 38
9.4.1
9.4.2
9.4.3
9.4.4
DATA STRUCTURES ....................................................................... 38
DMA TRANSACTION CONTROLLER ............................................. 48
WRITE DATA PIPELINE/MUX.......................................................... 48
DESCRIPTOR INFORMATION CACHE........................................... 48
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i