Nexperia
PIMC31PA
50 V, 500 mA NPN/PNP Resistor-Equipped double Transistor; R1 = 1 kΩ, R2 = 10 kΩ
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Per transistor
VCBO
VCEO
VEBO
VI
collector-base voltage
open emitter
[1]
[1]
[1]
[1]
[1]
[2]
[3]
[4]
[5]
-
50
V
collector-emitter voltage open base
-
50
V
emitter-base voltage
input voltage
open collector
-
5
V
-5
-
10
V
IO
output current
500
360
550
510
730
mA
mW
mW
mW
mW
Ptot
total power dissipation
Tamb ≤ 25 °C
-
-
-
-
Per device
Ptot
total power dissipation
Tamb ≤ 25 °C
[2]
[3]
[4]
[5]
-
500
750
700
1
mW
mW
mW
W
-
-
-
Tj
junction temperature
ambient temperature
storage temperature
-
150
150
150
°C
Tamb
Tstg
-55
-65
°C
°C
[1] For the PNP transistor with negative polarity.
[2] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided, 35 µm copper, tin-plated and standard footprint.
[3] Device mounted on an FR4 PCB, single-sided, 35μm copper, tin-plated; mounting pad for collector 1 cm2.
[4] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
[5] Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm2.
aaa-037263
1.2
P
tot
(W)
(1)
0.8
(2)
(3)
(4)
0.4
0
-75
-25
25
75
125
175
(°C)
T
amb
(1) FR4 PCB, 4-layer copper, 1 cm2
(2) FR4 PCB, single-sided, 35μm copper, 1 cm2
(3) FR4 PCB, 4-layer copper, standard footprint
(4) FR4 PCB, single-sided, 35μm copper, standard footprint
Fig. 1. Per device: Power derating curves for DFN2020-6 (SOT1118)
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PIMC31PA
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Nexperia B.V. 2023. All rights reserved
Product data sheet
31 August 2023
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