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PIMC31-Q PDF预览

PIMC31-Q

更新时间: 2023-09-03 20:28:05
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
11页 258K
描述
500 mA, 50 V NPN/PNP double resistor-equipped transistor; R1 = 1 kΩ, R2 = 10 kΩProduction

PIMC31-Q 数据手册

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Nexperia  
PIMC31-Q  
500 mA, 50 V NPN/PNP double resistor-equipped transistor; R1 = 1 kΩ, R2 = 10 kΩ  
5. Pinning information  
Table 2. Pinning information  
Pin  
1
Symbol  
GND1  
I1  
Description  
Simplified outline  
Graphic symbol  
O1 I2  
GND2  
TR2  
GND (emitter) TR1  
input (base) TR1  
output (collector) TR2  
GND (emitter) TR2  
input (base) TR2  
output (collector) TR1  
2
6
5
4
3
3
O2  
R1  
R2  
4
GND2  
I2  
TR1  
R2  
5
R1  
1
2
6
O1  
TSOP6 (SOT457)  
GND1  
I1 O2  
aaa-007379  
6. Ordering information  
Table 3. Ordering information  
Type number  
Package  
Name  
Description  
Version  
SOT457  
PIMC31-Q  
TSOP6  
plastic, surface-mounted package (SC-74; TSOP6); 6  
leads  
7. Marking  
Table 4. Marking codes  
Type number  
Marking code  
ZH  
PIMC31-Q  
8. Limiting values  
Table 5. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
Per transistor  
VCBO  
Parameter  
Conditions  
Min  
Max  
Unit  
collector-base voltage  
open emitter  
[1]  
[1]  
[1]  
-
50  
50  
5
V
VCEO  
collector-emitter voltage open base  
-
V
VEBO  
emitter-base voltage  
input voltage  
open collector  
TR1 (NPN)  
TR2 (PNP)  
-
V
VI  
-5  
-10  
-
10  
5
V
V
IO  
output current  
[1]  
[2]  
500  
290  
mA  
mW  
Ptot  
total power dissipation  
Tamb ≤ 25 °C  
Tamb ≤ 25 °C  
-
Per device  
Ptot  
Tj  
total power dissipation  
junction temperature  
ambient temperature  
[2]  
-
420  
150  
150  
mW  
°C  
-
Tamb  
-55  
°C  
©
PIMC31-Q  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2023. All rights reserved  
Product data sheet  
20 April 2023  
2 / 11  
 
 
 
 

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