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PI6CB18401ZHIEX PDF预览

PI6CB18401ZHIEX

更新时间: 2024-11-23 15:47:51
品牌 Logo 应用领域
美台 - DIODES 驱动逻辑集成电路
页数 文件大小 规格书
17页 775K
描述
PLL Based Clock Driver,

PI6CB18401ZHIEX 技术参数

生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:23 weeks风险等级:1.56
Is Samacsys:N系列:6C
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-XQCC-N32
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE传播延迟(tpd):4.5 ns
座面最大高度:0.8 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:5 mm
Base Number Matches:1

PI6CB18401ZHIEX 数据手册

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A product Line of  
Diodes Incorporated  
PI6CB18401  
Very Low Power 4-Output PCIe Clock Buffer With On-chip Termination  
Features  
Description  
Î1.8V supply voltage  
e PI6CB18401 is an 4-output very low power PCIe Gen1/Gen2/  
Gen3/Gen4 clock buffer. It takes an reference input to fanout four  
100MHz low power differential HCSL outputs with on-chip ter-  
minations. e on-chip termination can save 16 external resistors  
and make layout easier. Individual OE pin for each output pro-  
vides easier power management.  
ÎHCSL input: 100MHz, also suppport 50MHz or 125MHz via  
SMBus  
Î4 differential low power HCSL outputs with on-chip  
termination  
ÎIndividual output enable  
ÎProgrammable Slew rate and output amplitute for each  
It uses Pericom proprietary PLL design to achieve very low jit-  
ter that meets PCIe Gen1/Gen2/Gen3/Gen4 requirements. Other  
than PCIe 100MHz support, this device also support Ethernet ap-  
plication with 50MHz or 125MHz via SMBus. It provides various  
options such as different slew rate and amplitude through strap-  
ping pins or SMBUS so that users can configure the device easily  
to get the optimized performance for their individual boards.  
output  
ÎDifferential outputs blocked until PLL is locked  
ÎStrapping pins or SMBus for configuration;  
Î3.3V tolerant SMBus interface support  
ÎVery low jitter outputs  
yÎDifferential cycle-to-cycle jitter <50ps  
yÎDifferential output-to-output skew <50ps  
yÎPCIe Gen1/Gen2/Gen3/Gen4 compliant  
ÎPackaging (Pb-free & Green): 32-lead 5×5mm TQFN  
Block Diagram  
OE[3:0]#  
Q3  
Q2  
Q1  
Q0  
IN+  
PLL  
IN-  
SCLK  
SDATA  
SADR_TRI  
CTRL  
BW_SEL_TRI  
LOGIC  
PD#  
www.diodes.com  
January 2018  
Diodes Incorporated  
PI6CB18401  
Document Number DS40617 Rev 1-2  
1

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