Datasheet > PI6CDBL402B

PI6CDBL402B

更新时间： 2024-11-24 01:12:23

品牌	Logo	应用领域
百利通 - PERICOM		PC
页数	文件大小	规格书
13页	934K
描述
4 -Output Low Power PCIE GEN 1-2-3 Buffer

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PI6CDBL402B 数据手册

PI6CDBL402B

4 -Output Low Power PCIE GEN 1-2-3 Buffer

Description

Features

Pericom Semiconductor's PI6CDBL402B is a PCIe 3.0 compliant

high-speed, low-noise diﬀerential clock buﬀer designed to be

companion to PCIe 3.0 clock generator. It is backward compat-

ible with PCIe 1.0 and 2.0 speciﬁcation.

ꢀÎPhase jitter ﬁlter for PCIe 3.0/ 2.0/ 1.0 application

ꢀÎLow power consumption with independent output power

supply 1.8V~3.3V

ꢀÎLow skew < 60ps

ꢀÎLow cycle-to-cycle jitter - 45ps (typ.) @100MHz

ꢀÎ< 1 ps additive RMS phase jitter

ꢀÎOutput Enable for all outputs

ꢀÎProgrammable PLL Bandwidth

ꢀÎ100 MHz PLL Mode operation

ꢀÎ1 - 400 MHz Bypass Mode operation

ꢀÎ3.3V Operation

e device distributes the diﬀerential SRC clock from PCIe 3.0

clock generator to four diﬀerential pairs of clock outputs either

with or without PLL. e clock outputs are controlled by input

selection of PWRDWN# and SMBus, SCLK and SDA.

ꢀÎPackaging (Pb-free and Green):

-28-Pin TSSOP (L28)

Block Diagram

Pin Configuration

DD_A

OE_INV

OE_0 & OE_3

SRC

SRC#

GND

GNDA

OE_INV

Output

Control

PWRDWN#

OUT0

OUT0#

VDDO

DDO

OUT1

OUT1#

SMBus

Controller

SCLK

SDA

OUT0

OUT0#

OE_0

OUT1

OUT1#

OUT3

OUT3#

OE_3

OUT2

OUT2#

OUT2

OUT2#

PLL/BYPASS#

OUT3

OUT3#

SRC

SRC#

DDO

/B/B

PLL_BW#

PWRDWN#

PLL_BW#

SCLK

SDA

PLL

All trademarks are property of their respective owners.

www.pericom.com

06/30/15

15-0083

12 3 4 5 6 7...13

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