Datasheet > PI6CEQ20200LIE

PI6CEQ20200LIE

更新时间： 2024-10-02 01:04:59

品牌	Logo	应用领域
百利通 - PERICOM		PC
页数	文件大小	规格书
9页	875K
描述
PCIe Gen2 / Gen3 Buffer

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中文翻译

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数据手册

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PI6CEQ20200LIE 数据手册

PI6CEQ20200

PCIe® Gen2 / Gen3 Buﬀer

Features

Description

ꢀÎPCIe Gen2/ Gen3* compliant clock buﬀer/ZDB

* Gen3 performance only available in Commercial temp

^ꢀÎInternal equalization for better signal integrity

ꢀÎ2 HCSL outputs

e PI6CEQ20200 is a high performance PCIe Gen2/ Gen3

zero delay buﬀer with two HCSL outputs. Pericom’s proprietary

equalization technique used in this device improves signal

integrity and makes this device suitable for PCIe Gen2/ Gen3

applications even when the input from the main clock has to

travel a long distance.

ꢀÎDual PLL bandwidth for SSC tracking

ꢀÎCycle-to-Cycle Jitter : 40ps (typ)

ꢀÎOutput-to-Output Skew <10ps

ꢀÎ3.3V supply voltage

ꢀÎTSSOP-20 packages

Applications

ꢀÎServers

ꢀÎEmbedded computing systems

ꢀÎNetworking systems

Block Diagram

Pin Conﬁguration (20-Pin TSSOP & 20-Pin QSOP)

PLL_BW_SEL

SRCIN

SRCIN#

OE_0#

VDD

VDDA

GNDA

IRef

OE0#

CLK0

CLK0#

SRCIN

PLL

SRCIN#

OE_1#

VDD

OE1#

PLL_BW_SEL

SCLK

Control

CLK1

CLK1#

SDATA

GND

CLK0

CLK1

CLK1#

VDD

CLK0#

VDD

SDATA

SCLK

www.pericom.com

Rev B

05/05/15

15-0058

12 3 4 5 6 7...9

中文翻译

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